A latency tolerant code generation algorithm for a coarse grain dataflow machine

  • Stephan B. Murer
Large-Grain Data Flow
Part of the Lecture Notes in Computer Science book series (LNCS, volume 457)


First, a specific coarse-grain dataflow architecture, the ADAM-Architecture, is briefly introduced, highlighting the features which influence the language and compiler design of a high level language for this architecture. It is shown that the key requirement to hide latency leads to new code generation strategies.

In the main part of the paper, an algorithm is presented to generate sequential codeblocks for the ADAM-Architecture from dataflow graphs. We prove that the demonstrated algorithm generates correct code. Comparing the codes generated from the new algorithm and from a traditional leftmost depth-first code generator, the tradeoff between number of used registers and gained concurrency is discussed.

Finally, future research goals and the present state of work are demonstrated.


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  1. [1]
    Adam, T. L., K. M. Chandy and J. R. Dickson. “A Comparison of List Schedules for Parallel Processing Systems.” CACM 12, 12 (12-1974): 685ff.Google Scholar
  2. [2]
    Aho, A. V., Sethi, R., Ullman, J. D. Compilers Principles, Techniques and Tools. Addison-Wesley, 1986.Google Scholar
  3. [3]
    Andrews, G. R. and F. B. Schneider. “Concepts and Notations for Concurrent Programming.” Computing Surveys, The Survey and Tutorial Journal of the ACM 15, 1 (1983-3): 3ff.Google Scholar
  4. [4]
    Arvind and Culler D. E. “Dataflow Architectures”. Ann. Rev. Comput. Sci 1 (1986): 225–53.CrossRefGoogle Scholar
  5. [5]
    Arvind and R. A. Ianucci. “Two Fundamental Issues in Multiprocessing.” in Proceedings of DFVLR — Conference 1987 on Parallel Processing in Science and Engineering, Bonn-Bad Godesberg, D, 6-1987.Google Scholar
  6. [6]
    Bührer, R., Ekanadham, K., Incorporating Dataflow Ideas into von Neumann Processors for Parallel Execution, IEEE Trans. on Computers, C36(12):1515–1522, Dec. 1987.Google Scholar
  7. [7]
    Gurd, J. R., Kirkham, C. C., Watson, I. 1985. The Manchester dataflow prototype computer, CACM 28(1):34–52.Google Scholar
  8. [8]
    McMahon, F. H., L. L. N. L. FORTRAN Kernels: MFLOPS, Lawrence Livermore National Laboratory, 1986.Google Scholar
  9. [9]
    Maquelin, O. ADAM: a Coarse-Grain Dataflow Architecture that Adresses the Load Balancing and Throttling Problems, submitted to CONPAR 90.Google Scholar
  10. [10]
    Mitrovic, S. et al. “A Distributed Memory Multiprocessor Based on Dataflow Synchronization” in Proceedings of International Phoenix Conference on Computers and Communication, March 1990Google Scholar
  11. [11]
    Sarkar, V. Partitioning and Scheduling Parallel Programs for Multiprocessors. London: Pitman Publishers, 1989.Google Scholar
  12. [12]
    Skedzielewski S and Glauert J. IF1, An Intermediate Form for Applicative Languages, Lawrence Livermore Laboratory, 6-18-1984.Google Scholar
  13. [13]
    Wyttenbach, J. Design of a Variable Grain Dataflow Machine and its Relation to a New Approach for System Specification, Ph. D. Thesis, ETH Zürich (in preparation).Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1990

Authors and Affiliations

  • Stephan B. Murer
    • 1
  1. 1.Institut für Technische Informatik und KommunikationsnetzeETH ZürichZürichSwitzerland

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