Verifying the correctness of AADL modules using model checking
This paper presents a temporal logic MCTL which is suitable for modular specification and verification of computer architectures. MCTL has the advantage that open systems can be specified and verified; i.e. it allows the specification of properties under some assumptions on the environment. The module concept may help to solve the state explosion problem in the verification of temporal logic specifications. To verify the correctness of an implementation we describe a model checking algoritm for that logic.
Key wordstemporal logic expressiveness model checking modular specification verification computer architecture
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