Verification of synchronous sequential machines based on symbolic execution

  • Olivier Coudert
  • Christian Berthet
  • Jean Christophe Madre
Hardware Verification
Part of the Lecture Notes in Computer Science book series (LNCS, volume 407)


This paper presents an original method to compare two synchronous sequential machines. The method consists in a breadth first traversal of the product machine during which symbolic expressions of its observable behaviour are computed. The method uses formal manipulations on boolean functions to avoid the state enumeration and diagram construction. For this purpose, new algorithms on boolean functions represented by Typed Decision Graphs has been defined.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1990

Authors and Affiliations

  • Olivier Coudert
    • 1
  • Christian Berthet
    • 1
  • Jean Christophe Madre
    • 1
  1. 1.BULL Research CenterLouveciennesFrance

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