On restricted Boolean circuits

  • György Turán
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 380)


We consider some classes of restricted Boolean circuits: synchronous and locally synchronous circuits, planar circuits, formulas and multilective planar circuits. Bounds are given comparing the computational power of circuits from these classes.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    N. Alon, W. Maass: Meanders and their application in lower bounds arguments, J. Comp. Syst. Sci., 37(1988), 118–129.CrossRefGoogle Scholar
  2. [2]
    A. E. Andreev: On a method giving larger than quadratic effective lower bounds for the complexity of π-schemes, Vestnik Moscow Univ. Ser. 1 (Math. Mech.), 1986, No. 6, 73–76. (In Russian.)Google Scholar
  3. [3]
    L. Babai, P. Pudlák, V. Rödl, E. Szemerédi: Lower bounds to the complexity of symmetric functions, preprint (1986).Google Scholar
  4. [4]
    E. G. Belaga: Locally synchronous complexity in the light of the trans-box method, 1. STACS, LNCS 166(1984), 129–139.Google Scholar
  5. [5]
    E. G. Belaga: Constructive universal algebra: an introduction, Theor. Comp. Sci., 51(1987), 229–238.CrossRefGoogle Scholar
  6. [6]
    E. G. Belaga: Through the mincing machine with a Boolean layer cake, preprint (1987).Google Scholar
  7. [7]
    E. G. Belaga: Through the mincing machine with a Boolean layer cake. Non-standard computations over Boolean circuits in the lower-bounds-to-circuit-size complexity proving, Acta Inf., 26(1989), 381–407.Google Scholar
  8. [8]
    S. N. Bhatt, F. T. Leighton: A framework for solving VLSI graph layout problems, J. Comp. Syst. Sci., 28(1984), 300–343.CrossRefGoogle Scholar
  9. [9]
    O. Gabber, Z. Galil: Explicit construction of linear size superconcentrators, J. Comp. Syst. Sci., 22(1981), 407–420.CrossRefGoogle Scholar
  10. [10]
    L. H. Harper: An n log n lower bound on synchronous combinational complexity, Proc. AMS, 64(1977), 300–306.Google Scholar
  11. [11]
    L. H. Harper, J. E. Savage: Lower bounds on synchronous combinational complexity, SIAM J. Comp., 8(1979), 115–119.CrossRefGoogle Scholar
  12. [12]
    P. Hochschild: Multiple cuts, input repetition, and VLSI complexity, Inf. Proc. Lett., 24(1987), 19–24.CrossRefGoogle Scholar
  13. [13]
    Z. M. Kedem: Optimal allocation of computational resources in VLSI, 23 FOCS (1982), 379–385.Google Scholar
  14. [14]
    Z. M. Kedem, A. Zorat: Replication of inputs may save computational resources in VLSI, in: H. T. Kung, R. Sproull, G. Steele (eds.): VLSI Systems and Computations, Comp. Sci. Press (Rockwille, Md.), 1981, 52–60.Google Scholar
  15. [15]
    Z. M. Kedem, A. Zorat: On relations between input and communication/computation in VLSI, 22 FOCS (1981), 37–41.Google Scholar
  16. [16]
    R. J. Lipton, R. E. Tarjan: A planar separator theorem, SIAM J. Appl. Math., 36(1979), 177–189.CrossRefGoogle Scholar
  17. [17]
    R. J. Lipton, R. E. Tarjan: Applications of a planar separator theorem, SIAM J. Comp., 9(1980), 513–524.CrossRefGoogle Scholar
  18. [18]
    W. Maass, G. Schnitger: An optimal lower bound for Turing machines with one work tape and a two-way input tape, Structure in Complexity, LNCS 223(1986), 249–264.Google Scholar
  19. [19]
    W. Maass, G. Schnitger, E. Szemerédi: Two tapes are better than one for off-line Turing machines, 19 STOC (1987), 94–100.Google Scholar
  20. [20]
    W. F. McColl: Planar circuits have short specifications, STACS, LNCS 182 (1985), 231–242.Google Scholar
  21. [21]
    W. J. Paul: A 2.5n lower bound on the combinational complexity of Boolean functions, SIAM J. Comp., 6(1977), 427–443.CrossRefGoogle Scholar
  22. [22]
    J. E. Savage: Planar circuit complexity and the performance of VLSI algorithms, in: H. T. Kung, R. Sproull, G. Steele (eds.): VLSI Systems and Computations, Comp. Sci. Press (Rockwille, Md.), 1981, 61–67. Also: INRIA Report No. 77 (1981).Google Scholar
  23. [23]
    J. E. Savage: The performance of multilective VLSI algorithms, J. Comp. Syst. Sci., 29(1984), 243–272.Google Scholar
  24. [24]
    A. L. Toom: On the complexity of the realization of binary functions having few “subfunctions”, Problems of Cybernetics, 18(1967), 83–90. (In Russian.)Google Scholar
  25. [25]
    Gy. Turán: Lower bounds for synchronous circuits and planar circuits, Inf. Proc. Lett., 30(1989), 37–40.Google Scholar
  26. [26]
    D. Uhlig: On the relationship between circuit complexity of a Boolean functions and the number of its subfunctions, Problems of Cybernetics, 26(1973), 183–201. (In Russian.)Google Scholar
  27. [27]
    J. D. Ullman: Computational Aspects of VLSI, Comp. Sci. Press (Rockwille, Md.) (1984).Google Scholar
  28. [28]
    I. Wegener: The Complexity of Boolean Functions, Wiley-Teubner Series in Comp. Sci. (1987).Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1989

Authors and Affiliations

  • György Turán
    • 1
    • 2
  1. 1.Automata Theory Research Group of the Hungarian Academy of SciencesSzeged
  2. 2.Department of Mathematics, Statistics, and Computer ScienceUniversity of Illinois at ChicagoChicago

Personalised recommendations