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Formal Verification and Hardware Design with Statecharts

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Book cover Prospects for Hardware Foundations

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1546))

Abstract

Statecharts extend the concept of Mealy Machines by parallel composition, hierarchy, and broadcast communication. While Statecharts in principle are widely accepted in industry, some semantical concepts, especially broadcasting, are still contested. In this contribution, we present a Statechart dialect that includes the basic concepts of the language and present a formal, relational semantics for it. We show that this semantics can be used for both formal verification by model checking and hardware synthesis

This work has been partially sponsored by the NADA Esprit Working Group 8533 and the BMBF project “KorSys”.

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Authors and Affiliations

  1. Institut für Informatik, Technische Universität München, D-80290, München, Germany

    Jan Philipps & Peter Scholz

Authors
  1. Jan Philipps
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  2. Peter Scholz
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Editor information

Editors and Affiliations

  1. Department of Computer Science, University of Augsburg, Universitätsstr. 14, D-86135, Augsburg, Germany

    Bernhard Möller

  2. Department of Computer Science, University of Wales at Swansea, Singleton Park, Swansea, SA2 8PP, Wales, UK

    John V. Tucker

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© 1998 Springer-Verlag Berlin Heidelberg

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Philipps, J., Scholz, P. (1998). Formal Verification and Hardware Design with Statecharts. In: Möller, B., Tucker, J.V. (eds) Prospects for Hardware Foundations. Lecture Notes in Computer Science, vol 1546. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49254-2_11

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  • DOI: https://doi.org/10.1007/3-540-49254-2_11

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  • Print ISBN: 978-3-540-65461-2

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