Abstract
In this paper, we design a flexible VLSI-based parallel processing system for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the proposed architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Koga T., Iinuma K., Hirano A., Iijima Y. and Ishiguro T.: Motion-compensated interframe coding for video conferencing, Proceedings of National Telecommunication Conference, pp. G5.3.1–G5.3.5, New Orleans, LA, USA November 1981.
Li R., Zeng B. and Liou M.L.: A new three-step search algorithm for fast block motion estimation, IEEE trans. on Circuits and System for Video Technology4, 438–442 1994.
Booth W., Noras J.M.and Xu D.: A novel fast three-step search algorithm for blockmatching motion estimation. In: Chin R., Pong T.C. (eds.): Computer Vision. Lecture Notes in Computer Science, Vol. 1352. Springer-Verlag, Hong Kong 1998 623–630.
He Z., Liou M.L., Chan P.C.H. and Li R.: An efficient VLSI architecture for new threestep search algorithm, Proceedings of the 1995 IEEE 38th Midwest Symposium on Circuits and Systems, pp. 1228–1231, USA August 1995.
Gupta G. and Chakrabarti C.: Architectures for hierarchical and other block matching algorithms, IEEE Transactions on Circuits and Systems for Video Technology 5, 477–489 1995
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Xu, D., Sotudeh, R. (1999). A Flexible VLSI Parallel Processing System for Block-Matching Motion Estimation in Low Bit-Rate Video Coding Applications. In: Zinterhof, P., Vajteršic, M., Uhl, A. (eds) Parallel Computation. ACPC 1999. Lecture Notes in Computer Science, vol 1557. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-49164-3_24
Download citation
DOI: https://doi.org/10.1007/3-540-49164-3_24
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-65641-8
Online ISBN: 978-3-540-49164-4
eBook Packages: Springer Book Archive