Abstract
We describe how three hardware components (two combinational and one pipelined) for computing the Fast Fourier Transform have been proved equivalent using an automatic combination of symbolic simulation, rewriting techniques, induction and theorem proving. We also give some advice on how to verify circuits operating on complex data, and present a general purpose proof strategy for equivalence checking between combinational and pipelined circuits.
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© 1999 Springer-Verlag Berlin Heidelberg
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Bjesse, P. (1999). Automatic Verification of Combinational and Pipelined FFT Circuits. In: Halbwachs, N., Peled, D. (eds) Computer Aided Verification. CAV 1999. Lecture Notes in Computer Science, vol 1633. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48683-6_33
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DOI: https://doi.org/10.1007/3-540-48683-6_33
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