Efficient Timed Reachability Analysis Using Clock Difference Diagrams

  • G. Behrmann
  • K. G. Larsen
  • J. Pearson
  • C. Weise
  • W. Yi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1633)


One of the major problems in applying automatic verification tools to industrial-size systems is the excessive amount of memory required during the state-space exploration of a model. In the setting of real-time, this problem of state-explosion requires extra attention as information must be kept not only on the discrete control structure but also on the values of continuous clock variables.

In this paper, we exploit Clock Difference Diagrams, CDD’s, a BDD-like data-structure for representing and effectively manipulating certain non- convex subsets of the Euclidean space, notably those encountered during verification of timed automata.

A version of the real-time verification tool Uppaal using CDD’s as a compact data-structure for storing explored symbolic states has been implemented. Our experimental results demonstrate significant spacesavings: for eight industrial examples, the savings are in average 42% with moderate increase in runtime.

We further report on how the symbolic state-space exploration itself may be carried out using CDD’s.


Canonical Form Constraint System Symbolic State Reachability Analysis Symbolic Model Check 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1999

Authors and Affiliations

  • G. Behrmann
    • 1
  • K. G. Larsen
    • 1
  • J. Pearson
    • 2
  • C. Weise
    • 1
  • W. Yi
    • 2
  1. 1.BRICSAalborg UniversityDenmark
  2. 2.Dept. of Computer SystemsUppsala UniversitySweden

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