Abstract
One of the most important issues related to program performance is the memory hierarchy behavior. Programmers try nowadays to optimize this behavior intuitively or using costly techniques such as trace-driven simulations through a trial and error process. A systematic modeling strategy that allows an automated analysis of the memory hierarchy performance is developed in this work. This approach, besides requiring much shorter computation times, can be integrated in a compiler or an optimizing environment. The models consider caches of an arbitrary size, line size and associativity, and as we will show, they have proved a good degree of accuracy and have a wide range of applications. Loop interchange, loop fusion and optimal block size selection are the techniques whose successful application has been driven by the models in this work.
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Doallo, R., Fraguela, B.B., Zapata, E.L. (1999). Set Associative Cache Behavior Optimization⋆. In: Amestoy, P., et al. Euro-Par’99 Parallel Processing. Euro-Par 1999. Lecture Notes in Computer Science, vol 1685. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48311-X_28
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DOI: https://doi.org/10.1007/3-540-48311-X_28
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