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International Conference on Theorem Proving in Higher Order Logics

TPHOLs 1999: Theorem Proving in Higher Order Logics pp 113–130Cite as

A Machine-Checked Theory of Floating Point Arithmetic

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1690))

Abstract

Intel is applying formal verification to various pieces of mathematical software used in Merced, the first implementation of the new IA-64 architecture. This paper discusses the development of a generic floating point library giving definitions of the fundamental terms and containing formal proofs of important lemmas. We also briefly describe how this has been used in the verification effort so far.

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Author information

Authors and Affiliations

  1. Intel Corporation, EY2-03, 5200 NE Elam Young Parkway, Hillsboro, OR, 97124, USA

    John Harrison

Authors
  1. John Harrison
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Editor information

Editors and Affiliations

  1. INRIA Sophia Antipolis, 2004 Route des Lucioles, F-06902, Sophia Antipolis Cedex, France

    Yves Bertot , Gilles Dowek  & Laurent Théry ,  & 

  2. University of Nice - Sophia Antipolis, Parc Valrose, F-06108, Nice Cedex 2, France

    André Hirschowitz

  3. University of Paris XI, 15, rue Georges Clemenceau, F-91405, Orsay Cedex, France

    Christine Paulin

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© 1999 Springer-Verlag Berlin Heidelberg

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Harrison, J. (1999). A Machine-Checked Theory of Floating Point Arithmetic. In: Bertot, Y., Dowek, G., Théry, L., Hirschowitz, A., Paulin, C. (eds) Theorem Proving in Higher Order Logics. TPHOLs 1999. Lecture Notes in Computer Science, vol 1690. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-48256-3_9

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  • DOI: https://doi.org/10.1007/3-540-48256-3_9

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-66463-5

  • Online ISBN: 978-3-540-48256-7

  • eBook Packages: Springer Book Archive

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