Abstract
An attempt has been made to optimize the software energy of real time preemptive tasks by minimizing the cache related preemption costs which are primarily incurred due to the inter-task interference in the cache. We have presented an algorithm that outputs an ”optimum” task layout which reduces the overall inter-task interference in cache and thus reduces the preemption costs of each task of a given task set. We have compared the result of our estimated layout with that of the random layout generated for benchmark examples for demonstrating the performance of our algorithm.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Basumallick, S., Nilsen, K.: Cache Issues in Real-Time Systems. Proceedings of the 1st ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-time Systems, June 1994.
Busquets-Mataix, J.V., Serrano-Martin, J.J., Ors, R., Gil, P., Wellings, A.:Adding Instruction cache Effect to Schedulability Analysis of Preemptive Real-Time Systems”. Proceeding of the 2nd Real-Time Technology and Applications Symposium, June 1996.
Lee, C.G., Hahn, J., Seo, Y.M., Min, S.L., Ha, R., Hong, S., Park, C.Y., Lee, M., Kim, C.S.: Analysis of Cache Related Preemption Delay in fixed-priority Preemptive scheduling. IEEE Transactions on Computers, 47(6), June 1998.
Datta, A., Choudhury, S., Basu, A., Tomiyama, H., Dutt, N.: Task Layout Generation To Minimize Cache Miss Penalty For Preemptive Real Time tasks: An ILP Approach. Proceedings of the ninth Workshop on Synthesis And System Integration of Mixed Technologies (SASIMI), pp. 202–208, April 2000
Tiwary, V., Malik, S., Wolfe, A. Power Analysis of Embedded Software: A First Step Towards Software Power Minimization. IEEE Transactions on VLSI systems, December 1994.
Lee, M.T., Tiwary, V., Malik, S., Fujita, M.:Power analysis and Minimization Techniques for Embedded DSP Software. IEEE Transactions on VLSI Systems, December 1996.
Patra, T., Kumar, R., Basu, A.: Cache Size Optimization For Minimizing Software Energy in Embedded Systems. Proceedings of International Conference in Communications, Computers and Devices(ICCCD), pp262–266, December 2000.
Shuie, W.T., Chakraborty, C: Memory Exploration for Low Power Embedded Systems. Proceeding of 36th ACM/IEEE Design Automation Conference, June 1999.
Shin, Y., Choi, K.:Power Conscious Fixed Priority Sheduling for Hard Real-Time systems. Proceeding of 36th ACM/IEEE Design Automation Conference, June 1999.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kumar, R., Patra, T.K., Basu, A. (2002). Software Energy Optimization of Real Time Preemptive Tasks by Minimizing Cache-Related Preemption Costs. In: Zima, H.P., Joe, K., Sato, M., Seo, Y., Shimasaki, M. (eds) High Performance Computing. ISHPC 2002. Lecture Notes in Computer Science, vol 2327. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-47847-7_28
Download citation
DOI: https://doi.org/10.1007/3-540-47847-7_28
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-43674-4
Online ISBN: 978-3-540-47847-8
eBook Packages: Springer Book Archive