Abstract
In this paper, we present a Branch Target Buffer (BTB) design for energy savings in set-associative instruction caches. We extend the functionality of a BTB by caching way predictions in addition to branch target addresses. Way prediction and branch target prediction are done in parallel. Instruction cache energy savings are achieved by accessing one cache way if the way prediction for a fetch is available. To increase the number of way predictions for higher energy savings, we modify the BTB management policy to allocate entries for non-branch instructions. Furthermore, we propose to partition a BTB into ways for branch instructions and ways for non-branch instructions to reduce the BTB energy as well.
We evaluate the effectiveness of our BTB design and management policies with SPEC95 benchmarks. The best BTB configuration shows a 74% energy savings on average in a 4-way set-associative instruction cache and the performance degradation is only 0.1&. When the instruction cache energy and the BTB energy are considered together, the average energy-delay product reduction is 65%.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
K.B. Normoyle et al. UltraSparc-IIi: expanding the boundaries of system on a chip. IEEE Trans. Micro, 18(2):14–24, 1998.
Advanced Micro Devices, Inc. AMD athlon processor architecture, 2000. White paper.
D. H. Albonesi. Selective cache ways: on-demand cache resource allocation. In Int’l Symp. Microarchitecture, pages 248–259, 1999.
N. Bellas, I. Hajj, and C. Polychronopoulos. Using dynamic cache management techniques to reduce energy in a high-performance processor. In Int’l Symp. on Low Power Electronics and Design, pages 64–69, 1999.
D. Brooks, V. Tiwari, and M. Martonosi. Wattch: a framework for architectural-level power analysis and optimizations. In Int’l Symp. Computer Architecture, pages 83–94, 2000.
D. Burger and T. Austin. The simplescalar toolset, version 2.0. Technical Report TR-97-1342, University of Wisconsin-Madison, 1997.
M. Check and T. Slegel. Custom S/390 G5 and G6 microprocessors. IBM Journal of Research and Development, 43(5/6):671–680, 1999.
G. Hinton et al. The microarchitecture of the pentium 4 processor. Intel Technology Journal, Q1, 2001.
K. Ghose and M. Kamble. Reducing power in superscalar processor caches using subbanking, multiple line buffers and bit-line segmentation. In Int’l Symp. on Low Power Electronics and Design, pages 70–75, 1999.
K. Inoue, T. Ishihara, and K. Murakami. Way-predicting set-associative cache for high performance and low energy consumption. In Int’l Symp. on Low Power Electronics and Design, pages 273–275, 1999.
J. Montanaro et al. A 160-MHz, 32-b, 0.5-W CMOS RISC microprocessor. IEEE Journal of Solid-State Circuits, 32(11):1703–14, 1996.
R. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2):24–36, 1999.
J. Kin, M. Gupta, and W. Mangione-Smith. The filter cache: An energy efficient memory structure. In Int’l Symp. Microarchitecture, pages 184–193, 1997.
S. Manne, A. Klauser, and D. Grunwald. Pipeline gating: speculation control for energy reduction. In Int’l Symp. Computer Architecture, pages 132–141, 1998.
E. Musoll. Predicting the usefulness of a block result: a micro-architectural technique for high-performance low-power processors. In Int’l Symp. Microarchitecture, pages 238–247, 1999.
C. Perleberg and A. Smith. Branch target buffer design and optimization. IEEE Trans. Computers, 42(4):396–412, 1993.
S. Wilton and N. Jouppi. An enhanced access and cycle time model for on-chip caches. Technical Report 93/5, Digital Western Research Laboratory, 1994.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Tang, W., Veidenbaum, A., Nicolau, A., Gupta, R. (2002). Integrated I-cache Way Predictor and Branch Target Buffer to Reduce Energy Consumption. In: Zima, H.P., Joe, K., Sato, M., Seo, Y., Shimasaki, M. (eds) High Performance Computing. ISHPC 2002. Lecture Notes in Computer Science, vol 2327. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-47847-7_12
Download citation
DOI: https://doi.org/10.1007/3-540-47847-7_12
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-43674-4
Online ISBN: 978-3-540-47847-8
eBook Packages: Springer Book Archive