Abstract
This paper presents a high-level temporal partitioning algorithm, which is able to split the VHDL description of a digital system into two equivalent subdescriptions. The primary goal of the algorithm is to obtain two area-balanced, time-independent partitions. The descriptions of these partitions can be separately simulated, synthesized and implemented as different configurations of a dynamically reconfigurable device. The partitioning principle is based on a directed task hypergraph. Each vertex of this hypergraph corresponds to one concurrent assignment of the description being analysed. The resources required for the physical implementation of each vertex are calculated by means of a simplified resource estimator. Time dependencies between vertices are denoted by hyperedges representing signals connecting appropriate concurrent assignments.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
de Micheli, G.: Synthesis and Optimisation of Digital Circuits. McGraw-Hill, 1994
Canto, E., Moreno, J.M., Cabestany, J., Lacadena, I., Insenser, J.M.: A Temporal Bipartitioning Algorithm for Dynamically Reconfigurable FPGAs. IEEE Transactions on Very Large Scale Integration (VLSI) systems, Vol. 9, No. 1., pp. 210–218, February 2001
Canto, E.: Temporal Bipartitioning Techniques for Multi-context FPGAs. Ph.D. Thesis, Universitat Politecnica de Catalunya, July 2001
Kaul, M., Vemuri, R.: Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs. Proceedings on Design, Automation and Test in Europe (DATE’99), IEEE Computer Society Press, pp. 202–209, March 1999
Maestre, R., Kurdahi, F.J., Fernandes, M., Hermida, R., Bagherzadeh, N., Singh, H.: A Framework for Reconfigurable Computing: Task Scheduling and Context Management. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 9, No. 6, pp. 858–873, December 2001
Bhat, N.B., Chaudhary, K., Kuh, E.S.: Performance-Oriented Fully Routable Dynamic Architecture for a Field Programmable Logic Device. UCB/ERL M93/42, University of California, Berkley, June 1993
DeHon, A.: Reconfigurable Architectures for General-Purpose Computing. Ph.D. Thesis, Massachusetts Institute of Technology, October 1996
Trimberger, S.: A Time Multiplexed FPGA. Proceedings FPGAs for Custom Computing Machines (FCCM’97), IEEE Computer Society, 1997
Faura, J., Horton, C., van Doung, P., Madrenas, J., Insenser, J.M.: A Novel Mixed Signal Programmable Device with On-Chip Microprocessor. Proceedings of the IEEE 1997 Custom Integrated Circuits Conference, pp.103–106
Faura, J., Moreno, J.M., Aguirre, M-A., van Doung, P., Insenser, J.M.: FIPSOC: A Filed Programmable System On a Chip. Proceedings of the XII Design of Circuits and Integrated Systems Conference (DCIS’97), pp. 597–602, Sevilla, November 1997
Fiduccia, C.M., Mattheyses, R.M.: A Linear-Time Heuristic Procedure for Improved Network Partitions. Proceedings on Design Automation Conference, pp. 241–247, 1982
Enzler, R., Jeger, T., Cottet, D., Tröster, G.: High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs. Proceedings of FPL 2000, pp. 525–534, Springer-Verlag, 2000
Machado, F., Torroja, Y., Casado, F., Riesgo, T., de la Torre, E., Uceda, J.: A Simple Method to Estimate the Area of VHDL RTL descriptions. Proceedings of the XV Design of Circuits and Integrated Systems Conference (DCIS 2000), Montpellier, November 2000
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2002 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Kielbik, R., Moreno, J.M., Napieralski, A., Jablonski, 1., Szymanski, T. (2002). High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_29
Download citation
DOI: https://doi.org/10.1007/3-540-46117-5_29
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-44108-3
Online ISBN: 978-3-540-46117-3
eBook Packages: Springer Book Archive