Abstract
This paper describes a new iterative method based on an integrated timing-driven approach to the FPGA layout synthesis. The method uses a global routing to assess the quality of a placement. The placement and routing algorithms use a unified nonlinear cost function that takes into account both area and delay constraints imposed by a design, and eliminates effects of different signal net routing orders.
This research has been partially supported by the Czech Technical University under grant no. CTU0210413
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References
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Daněk, M., Muzikář, Z.: Integrated Timing-Driven Approach to the FPGA Layout. To appear in: ICECS 2002 Proceedings, IEEE Press, 2002.
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Daněk, M., Muzikář, Z. (2002). Integrated Iterative Approach to FPGA Placement. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_27
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DOI: https://doi.org/10.1007/3-540-46117-5_27
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