Abstract
A method for implementing bit-serial Finite Impulse Response (FIR) filters in Field Programmable Gate Arrays (FPGA) using JBits™ to generate FPGA configuration bitstreams is presented. Traditional general- purpose placement tools have been bypassed with a bit-serial FIR filter placement method that uses JBits to generate FPGA configuration bitstreams. The JBits™ based bit-serial FIR filter placement method takes advantage of next-neighbor connectivity of bit-serial arithmetic cores to reduce the length of interconnections between cores and increase packing density of the cores in the FPGA. A design example for a filter with finite-precision coefficients generated by a Peak-Constrained Least-Squares filter design method is presented.
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Carreira, A., Fox, T., Turner, L. (2002). A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits™. In: Glesner, M., Zipf, P., Renovell, M. (eds) Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream. FPL 2002. Lecture Notes in Computer Science, vol 2438. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-46117-5_24
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DOI: https://doi.org/10.1007/3-540-46117-5_24
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