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Image Filter Design with Evolvable Hardware

  • Lukáš Sekanina
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2279)

Abstract

The paper introduces a new approach to automatic design of image filters for a given type of noise. The approach employs evolvable hardware at simplified functional level and produces circuits that outperform conventional designs. If an image is available both with and without noise, the whole process of filter design can be done automatically, without influence of a designer.

Keywords

Genetic Program Training Image Programmable Element Conventional Design Evolutionary Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    Šonka, M., Hlaváč, V., Boyle R.: Image Processing, Analysis and Machine Vision. Chapman & Hall, University Press, Cambridge (1993)Google Scholar
  2. 2.
    Russ, J., C.: The Image Processing Handbook (third edition). CRC Press LLC (1999)Google Scholar
  3. 3.
    Sanchez, E., Tomassini, M. (Eds.): Towards Evolvable Hardware: The Evolutionary Engineering Approach. LNCS 1062, Springer-Verlag, Berlin (1996)Google Scholar
  4. 4.
    Torresen, J.: Possibilities and Limitations of Applying Evolvable Hardware to Real-World Applications. In: Proc. of the Field Programmable Logic and Applications FPL2000, LNCS 1896, Springer-Verlag, Berlin (2000) 230–239Google Scholar
  5. 5.
    Miller, J., Thomson, P.: Cartesian Genetic Programming. In: Proc. of the Genetic Programming European Conference EuroGP 2000, LNCS 1802, Springer-Verlag, Berlin (2000) 121–132Google Scholar
  6. 6.
    Miller, J., Job, D., Vassilev, V.: Principles in the Evolutionary Design of Digital Circuits-Part I. In: Genetic Programming and Evolvable Machines, Vol. 1(1), Kluwer Academic Publisher (2000) 8–35CrossRefGoogle Scholar
  7. 7.
    Murakawa, M. et al.: Evolvable Hardware at Function Level. In: Proc. of the Parallel Problem Solving from Nature PPSN IV, LNCS 1141, Springer-Verlag Berlin (1996) 62–72Google Scholar
  8. 8.
    Hollingworth, G., Tyrrell, A., Smith S.: Simulation of Evolvable Hardware to Solve Low Level Image Processing Tasks. In: Proc. of the Evolutionary Image Analysis, Signal Processing and Telecommunications Workshop EvoIASP’99, LNCS 1596 Springer-Verlag, Berlin (1999) 46–58Google Scholar
  9. 9.
    Dumoulin, J. et al.: Special Purpose Image Convolution with Evolvable Hardware. In: Proc. of the EvoIASP 2000Workshop, Real-World Applications of Evolutionary Computing, LNCS 1803, Springer-Verlag, Berlin (2000) 1–11Google Scholar
  10. 10.
    Harvey. N, Marshall, S.: GA Optimization of Spatio-Temporal Gray-Scale Soft Morphological Filters with Applications in Archive Film Restoration. In: Proc. of the Evolutionary Image Analysis, Signal Processing and Telecommunications Workshop EvoIASP’99, LNCS 1596 Springer-Verlag, Berlin (1999) 31–45Google Scholar
  11. 11.
    Miller, J.: Evolution of Digital Filters Using a Gate Array Model. In: Proc. of the Evolutionary Image Analysis, Signal Processing and Telecommunications Workshop EvoIASP’99, LNCS 1596 Springer-Verlag, Berlin (1999) 17–30Google Scholar
  12. 12.
    Tufte, G., Haddow, P.: Evolving an Adaptive Digital Filter. In: Proc of the Second NASA/DoD Workshop on Evolvable Hardware, IEEE Computer Society, Los Alamitos (2000) 143–150Google Scholar
  13. 13.
    Koza, J. et al.: Genetic Programming III: Darwinian Invention and Problem Solving. Morgan Kaufmann Publishers (1999)Google Scholar
  14. 14.
    Erba, M. et al.: An Evolutionary Approach to Automatic Generation of VHDL Code for Low-Power Digital Filters. In: Proc. of the Genetic Programming European Conference EuroGP 2001, LNCS 2038, Springer-Verlag, Berlin (2001) 36–50Google Scholar
  15. 15.
    Sekanina, L., Sllame, A.: Toward Uniform Approach to Design of Evolvable Hardware Based Systems. In: Proc. of the Field Programmable Logic And Applications FPL 2000, LNCS 1896, Springer-Verlag, Berlin (2000) 814–817Google Scholar
  16. 16.
    Sekanina, L., Rŭžička, R.: Design of the Special Fast Reconfigurable Chip Using Common FPGA. In: Proc. of the Design and Diagnostic of Electronic Circuits and Systems IEEE DDECS’2000, Polygrafia SAF Bratislava, Slovakia (2000) 161–168Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Lukáš Sekanina
    • 1
  1. 1.Faculty of Information TechnologyBrno University of TechnologyBrnoCzech Republic

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