Abstract
Power consumption is becoming one of the most important constraints for microprocessor design in nanometer-scale technologies. Device engineers, circuit designers, and system architects are faced with many challenges. In the area of mobile and embedded computer platforms, power has already been a major design constraint. However, it is also a limiting issue in general-purpose microprocessors. In order to manage the impact of increasing microprocessor power consumption, some architectural-level techniques are required as well as circuit-level design improvements. In this paper, we propose to make any instruction in the program execution flow non-critical by using a low-cost value predictor in order to improve energy efficiency. Based on simulations, we find that up to 11.4% of energy reduction in functional units can be attained by utilizing value prediction.
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References
Burger D., Austin T.M.: The SimpleScalar tool set, version 2.0. ACM SIGARCH Computer Architecture News, 25(3) (1997)
Calder B., Reinman G., Tullsen D.M.: Selective value prediction. 26th Int. Symp. on Computer Architecture (1999)
Casmira J., Grunwald D.: Dynamic instruction scheduling slack. Kool ChipsWorkshop (2000)
Fields B.A., Rubin S., Bodik R.: Focusing processor policies via critical-path prediction. 28th Int. Symp. on Computer Architecture (2001)
Hashimoto M., Onodera H.: Post-layout transistor sizing for power reduction in cell-based design. IEICE Trans. Fundamentals, E84-A(11) (2001)
Hiramoto T., Takamiya M.: Low power and low voltage MOSFETs with variable threshold voltage controlled by back-bias. IEICE Trans. Electronics, E83-C(2) (2000)
Intel Corporation: Intel(R) XScaleTM technology. http://developer.intel.com/design/intelxscale/ (2002)
Lee C., Potkonjak M., Mangione-Smith W.H.: MediaBench: a tool for evaluating and synthesizing multimedia and communications systems. 30th Int. Symp. on Microarchitecture (1997)
Levy M: Java to go: part 1: Microprocessor Report, 15(2) (2001)
Levy M. NEC processor goes out of order. Microprocessor Report, 15(9) (2001)
Lipasti M.H., Wilkerson C.B., Shen J.P.: Value locality and load value prediction. 7th Int. Conf. on Architectural Support for Programming Languages and Operation Systems (1996)
Morancho E., Llaberia J.M., Olive A.: Split last-address predictor. 8th Int. Conf. on Parallel Architectures and Compilation Techniques (1998)
Pyreddy R., Tyson G.: Evaluating design tradeoffs in dual pipelines. Workshop on Complexity-Effective Design (2001)
Sato T.: Evaluating the impact of reissued instructions on data speculative processor performance. Microprocessors and Microsystems, 25(9–10) (2002)
Sato T., Koushiro T., Chiyonobu A., Arita I.: Power and performance fitting in nanometer design. 5th Int. Workshop on Innovative Architecture for Future Generation High-Performance Processors and Systems (2002)
Sato T., Arita I.: Low-cost value predictors using frequent value locality. 4th Int. Symp. on High Performance Computing, LNCS2327 (2002)
Seng J.S., Tune E.S., Tullsen D.M.: Reducing power with dynamic critical path information. 34th Int. Symp. on Microarchitecture (2001)
Transmeta corporation: CrusoeTM processor model TM5800. Product Brief (2001)
Tune E., Liang D., Tullsen D.M., Calder B.: Dynamic prediction of critical path instructions. 7th Int. Symp. on High Performance Computer Architecture (2001)
Usami K., Horowiz M.: Clustered voltage scaling technique for low-power design. Int. Symp. on Low Power Design (1995)
Wang K., Franklin M.: Highly accurate data value prediction using hybrid predictors. 30th Int. Symp. on Microarchitecture (1997)
Wet L., Chen Z., Johnson M., Roy K.: Design and optimization of low voltage and high performance dual threshold CMOS circuits. Int. Design Automation Conf. (1998)
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Sato, T., Arita, I. (2002). Reducing Energy Consumption via Low-Cost Value Prediction. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_38
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DOI: https://doi.org/10.1007/3-540-45716-X_38
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