Abstract
In this communication, an approach to analytically estimate the energy consumption in RC ladder circuits is proposed. Effect of the input rise time on energy dissipated is modeled by assuming a ramp input. The approach is based on an exact analysis of energy dissipated by the network for asymptotic values of the input rise time. Successively, starting from the RC ladder circuits properties, a generalization is provided for arbitrary values of the input rise time. The approach followed leads to a closed-form expression of the energy dissipation. Moreover, this expression is formally equal to that of a first-order RC circuit, and is thus simple enough to be used for pencil-and-paper evaluation. The accuracy of the model has been tested by SPICE simulations. Results show that the energy predicted is in good agreement with simulated values.
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References
E. Sànchez-Sincencio, in Low-Voltage/Low-Power Integrated Circuits and Systems, E. Sànchez-Sincencio, A. Andreou (Eds.), IEEE Press, 1999.
A. Chandrakasan, R. Brodersen, in Low Power Digital CMOS Design, A. Chandrakasan, R. Brodersen (Eds.), Kluwer Academic Publisher, 1995.
K. Roy, S. Prasad, Low-Power CMOS VLSI Circuit Design, Wiley Interscience, 2000.
W. Athas, “Energy-Recovery CMOS,” in Low Power Digital Design Methodologies, J. Rabey, M. Pedram, Eds., Kluwer Academic Publisher, 1995.
R. Gupta, B. Tutuianu, L. Pileggi, “The Elmore Delay as a Bound for RC Trees with Generalized Input Signals,” IEEE Trans. on CAD, vol. 16, no. 1, Jan. 1997.
W. C. Elmore, “The transient response of damped linear networks with particular regard to wideband amplifiers,” J. Appl. Phys., vol.19, pp. 55–63, Jan. 1948.
J. Rubinstein, P. Penfield, Jr., and M. A. Horowitz, “Signal delay in RC tree networks,” IEEE Trans. on Computer-Aided Design, Vol. CAD-2, pp. 202–211, July 1983.
J. L. Wyatt, Jr., “Signal propagation delay in RC models for interconnect,” Circuit Analysis, Simulation and Design, Part II: VLSI Circuit Analysis and Simulation, A. Ruehli, ed., Vol. 3 in the series Advances in CAD for VLSI, North-Holland, 1987.
E. G. Friedman, J. H. Mulligan, Jr., “Ramp input response of RC tree networks,” Analog Integrated Circuits and Signal Processing, vol. 14, no. 1/2, pp.53–58, Sept. 1997
M. Celik, L. Pileggi, “Metrics and Bounds for Phase Delay and Signal Attenuation in RC(L) Clock Trees,” IEEE Trans. on Computer Aided-Design of Integrated Circuits and Systems, Vol. 18, No. 3, pp. 293–300, March 1999.
M. Alioto, G. Palumbo, “Power Estimation in Adiabatic Circuits: A Simple and Accurate Model,” IEEE Trans. on VLSI Systems, vol. 9, no. 5, pp. 608–615, October 2001.
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Alioto, M., Palumbo, G., Poli, M. (2002). An Approach to Energy Consumption Modeling in RC Ladder Circuits. In: Hochet, B., Acosta, A.J., Bellido, M.J. (eds) Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation. PATMOS 2002. Lecture Notes in Computer Science, vol 2451. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45716-X_24
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DOI: https://doi.org/10.1007/3-540-45716-X_24
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