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A Shogi Processor with a Field Programmable Gate Array

Part of the Lecture Notes in Computer Science book series (LNCS,volume 2063)

Abstract

In this paper we describe the architecture of a shogi processor based on reconfigurable hardware. For our implementation, we have used Field Programmable Gate Arrays (FPGAs), which can be reconfigured dynamically by downloading configuration data from host computers. Because of this reconfiguration flexibility, it is possible to implement and evaluate new algorithms quickly and to make small subsystems (of very low cost) that can be used on demand. For shogi these two features are especially important, as there are no stable subsystems that can be ported to special purpose hardware. Also, in shogi different modules are needed for different stages of the game. To test the feasibility of using FPGAs for shogi, we have implemented two modules that are general for all strong shogi programs on one off-the-shelf PCI board with one FPGA. The piece cover module on an FPGA is 62 times faster than the software module, while the module for finding mate on an FPGA is 9 times faster than the software module.

keywords

  • Reconfigurable hardware
  • FPGA
  • Shogi

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© 2001 Springer-Verlag Berlin Heidelberg

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Hori, Y., Seki, M., Maruyama, T., Grimbergen, R., Hoshino, T. (2001). A Shogi Processor with a Field Programmable Gate Array. In: Marsland, T., Frank, I. (eds) Computers and Games. CG 2000. Lecture Notes in Computer Science, vol 2063. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45579-5_20

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  • DOI: https://doi.org/10.1007/3-540-45579-5_20

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-43080-3

  • Online ISBN: 978-3-540-45579-0

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