Abstract
Debugging is a time-consuming task especially for larger programs written by a group of people. In this paper we describe the use of multiple models for debuggingVHDL designs, and presents some practical results. The models are derived from a general value-based model representing different fault situations that should be handled by a debugger.We propose the use of a probability-based selection strategy for selecting the most appropriate model in a given situation. For example large programs should be debugged using a model only distinguishing concurrent VHDL statements and not sequential statements. As a result of multi- model reasoning in this domain we expect performance gains allowing to debug larger designs in a reasonable time, and more expressive diagnosis results.
The work described in this paper was partially supported by the Austrian Science Fund project P12344-INF and project N Z29-INF.
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Wotawa, F. (2001). Using Multiple Models for Debugging VHDL Designs* . In: Monostori, L., Váncza, J., Ali, M. (eds) Engineering of Intelligent Systems. IEA/AIE 2001. Lecture Notes in Computer Science(), vol 2070. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45517-5_16
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DOI: https://doi.org/10.1007/3-540-45517-5_16
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