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Compiler Optimizations for Adaptive EPIC Processors

  • Krishna V. Palem
  • Surendranath Talla
  • Weng-Fai Wong
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2211)

Abstract

Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting ways in which this silicon may be used is to leave portions of it uncommitted and re-programmable depending on an applications needs. In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face. In this paper, we will elaborate on the compiler optimization issues involved. In particular, we will outline a framework for code partitioning, instruction synthesis, configuration selection, resource allocation, and instruction scheduling. Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources. The instruction synthesis phase generates suitable implementations for the candidates partitions and updates the machine description database with the new instructions. Configuration selection is the problem of narrowing down the choices of which synthesized instruction (from the set generated by the instruction synthesis phase) to use for each of the code regions that will be mapped to programmable logic. Unlike traditional optimizing compilers, the adaptive EPIC compiler must deal with the existence of synthesized instructions. Compilation techniques addressing each of these problems will be presented.

Keywords

Programmable Logic Field Programmable Gate Array Basic Block External Memory Logic Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Krishna V. Palem
    • 1
  • Surendranath Talla
    • 1
  • Weng-Fai Wong
    • 2
  1. 1.Center for Research on Embedded Systems and TechnologyGeorgia
  2. 2.Dept. of Computer ScienceNational University of SingaporeSingapore

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