Compiler Optimizations for Adaptive EPIC Processors

  • Krishna V. Palem
  • Surendranath Talla
  • Weng-Fai Wong
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2211)


Advances in VLSI technology have lead to a tremendous increase in the density and number of devices that can be manufactured in a single microchip. One of the interesting ways in which this silicon may be used is to leave portions of it uncommitted and re-programmable depending on an applications needs. In an earlier paper, we proposed a machine architecture for achieving this reconfigurability and compilation issues that such an architecture will face. In this paper, we will elaborate on the compiler optimization issues involved. In particular, we will outline a framework for code partitioning, instruction synthesis, configuration selection, resource allocation, and instruction scheduling. Partitioning is the problem of identifying code sections that may benefit by mapping them on to the programmable logic resources. The instruction synthesis phase generates suitable implementations for the candidates partitions and updates the machine description database with the new instructions. Configuration selection is the problem of narrowing down the choices of which synthesized instruction (from the set generated by the instruction synthesis phase) to use for each of the code regions that will be mapped to programmable logic. Unlike traditional optimizing compilers, the adaptive EPIC compiler must deal with the existence of synthesized instructions. Compilation techniques addressing each of these problems will be presented.


Programmable Logic Field Programmable Gate Array Basic Block External Memory Logic Design 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    Anant Agarwal, Saman Amarasinghe, Rajeev Barua, Matthew Frank, Walter Lee, Vivek Sarkar, Devabhaktuni Srikrishna,, and Michael Taylor. The RAW compiler project. In Proceedings of the Second SUIF Compiler Workshop, pages 21–23, Stanford, CA, August 1997.Google Scholar
  2. 2.
    P. M. Athanas and H. F. Silverman. Processor reconfiguration through instructionset metamorphosis. IEEE Computer, 26(3):11–18, March 1993.Google Scholar
  3. 3.
    P. Bertin, D. Roncin, and J. Vuillemin. Introduction to programmable active memories. In J. McCanny, J. McWhirther, and E. Swartslander Jr., editors, Systolic Array Processors, pages 300–309. Prentice Hall, 1989.Google Scholar
  4. 4.
    P. Bertin, D. Roncin, and J. Vuillemin. Programmable active memories: a performance assessment. In G. Borriello and C. Ebeling, editors, Research on Integrated Systems: Proceedings of the 1993Symposium, pages 88–102, 1993.Google Scholar
  5. 5.
    Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, and Donald E. Thomas. Managing pipeline-reconfigurable fpgas. In Proceedings ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, February 1998.Google Scholar
  6. 6.
    D. Callahan and B. Koblenz. Register allocation via hierarchical graph coloring. In Proceedings of the ACM SIGPLAN’ 91 Conference on Programming Language Design and Implementation, volume 26, pages 192–203, Toronto, Ontario, Canada, June 1991.Google Scholar
  7. 7.
    G. Chaitin, M. Auslander, A. Chandra, J. Cocke, M. Hopkins, and P. Markstein. Register allocating via coloring, 1981.Google Scholar
  8. 8.
    Gregory J. Chaitin. Register allocation and spilling via graph coloring. SIGPLAN Notices (Proceedings of the SIGPLAN’ 82 Symposium on Compiler Construction, Boston, Mass.), 17(6):98–105, 1982.CrossRefMathSciNetGoogle Scholar
  9. 9.
    F. Chow, K. Knobe, A. Meltzer, R. Morgan, and K. Zadeck. Register allocation.Google Scholar
  10. 10.
    Fred C. Chow and John L. Hennessy. Register allocation by priority-based coloring. In Proceedings of the ACM SIGPLAN 84 Symposium on Compiler Construction, pages 222–232, New York, NY, 1984. ACM.Google Scholar
  11. 11.
    G. Estrin. Organization of computer systems-the fixed plus variable structure computer. In Proceedings of the Western Joint Computer Conference, pages 33–40, 1960.Google Scholar
  12. 12.
    M. Gokhale, W. Holmes, A. Kopser, S. Lucas, R. Minnich, D. Sweely, and D. Lopresti. Building and using a highly parallel programmable logic array. IEEE Computer, 24(1):81–89, January 1991.Google Scholar
  13. 13.
    C. Ebeling D. C. Green and P. Franklin. RaPiD-reconfigurable pipelined datapath. In R. W. Hartenstein and M. Glesner, editors, Field-Programmable Logic: Smart Applications, New Paradigms, and Compilers. 6th International Workshop on Field-Programmable Logic and Applications, pages 126–135, Darmstadt, Germany, September 1996. Springer-Verlag.Google Scholar
  14. 14.
    S. Hauck, T. W. Fry, M. M. Hosler, and J. P. Kao. The chimaera reconfigurable functional unit. In IEEE Symposium on FPGAs for Custom Computing Machines, pages 87–96, 1997.Google Scholar
  15. 15.
    S. Hauck, M. M. Hosler, and T. W. Fry. High-performance carry chains for fpgas. In ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, pages 223–233, 1998.Google Scholar
  16. 16.
    John R. Hauser and John Wawrzynek. GARP: A MIPS processor with a reconfigurable coprocessor. In J. Arnold and K. L. Pocek, editors, Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, pages 12–21, Napa, CA, April 1997.Google Scholar
  17. 17.
    A. Kempe. The geographical problem of the four colors. Amer. J. Math. 2, 193–200., 1879.CrossRefMathSciNetGoogle Scholar
  18. 18.
    H. Kim and A. Leung. Frequency based live range splitting. Technical report, ReaCT-ILP Laboratory, New York University, 1999.Google Scholar
  19. 19.
    Walter Lee, Rajeev Barua, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman Amarasinghe, and Anant Agarwal. Space-time scheduling of instruction-level parallelism on a RAW machine. MIT/LCS Technical Memo TM-572, December 1997.Google Scholar
  20. 20.
    S. Muchnick. Advanced compiler design and implementation, 1997.Google Scholar
  21. 21.
    R. Razdan and M. D. Smith. A high-performance microarchitecture with hardwareprogrammable functional units. In Proceedings of the 27th Annual International Symposium on Microarchitecture, pages 172–80. IEEE/ACM, November 1994.Google Scholar
  22. 22.
    Rahul Razdan. PRISC: Programmable Reduced Instruction Set Computers. PhD thesis, Harvard University, May 1994.Google Scholar
  23. 23.
    Mario R. Schaffner. Processing by data and program blocks. IEEE Transactions on Computers, 27(11):1015–1028, November 1978.zbMATHCrossRefGoogle Scholar
  24. 24.
    M. Schlansker and B. Rau. EPIC: An architecture for instruction-level parallel processors. Technical report HPL-1999-111, Hewlett-Packard Laboratories, Technical Publications Department, 1501 Page Mill Road, Palo Alto, CA 94304., 2000.Google Scholar
  25. 25.
    S. Talla. Adaptive Explicitly Parallel Instruction Computing. PhD thesis, New York University, 2000.Google Scholar
  26. 26.
    Stephen M. Trimberger. Field-Programmable Gate Array Technology. Kluwer Academic Publishers, 1994.Google Scholar
  27. 27.
    Triscend Corp., Mountain View, U.S.A. Triscend A7 Configurable System-on-a-Chip Family Data Sheet, 2001.Google Scholar
  28. 28.
    John Villasenor and William H. Mangione-Smith. Configurable computing. Scientific American, pages 66–71, June 1997.Google Scholar
  29. 29.
    J. Vuillemin, P. Bertin, D. Roncin, M. Shand, H. Touati, and P. Boucard. Programmable active memories: Reconfigurable systems come of age. IEEE Transactions on VLSI Systems, 4(1):56–69, 1996.CrossRefGoogle Scholar
  30. 30.
    E. Waingold, M. Taylor, D. Srikrishna, V. Sarkar, W. Lee, V. Lee, J. Kim, M. Frank, P. Finch, R. Barua, J. Babb, S. Amarasinghe, and A. Agarwal. Baring it all to software: RAW machines. IEEE Computer, pages 86–93, September 1997.Google Scholar
  31. 31.
    M. J. Wirthlin and B. L. Hutchings. DISC: The dynamic instruction set computer. In J. Schewel, editor, Proceedings of the International Society of Optical Engineering (SPIE). Field Programmable Gate Arrays (FPGAs) for Fast Board Development and Reconfigurable Computing., volume 2607, pages 92–103, Philadephia, PA, 1995.Google Scholar
  32. 32.
    Xilinx, San Jose, CA. The Programmable Logic Data Book, 1994.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Krishna V. Palem
    • 1
  • Surendranath Talla
    • 1
  • Weng-Fai Wong
    • 2
  1. 1.Center for Research on Embedded Systems and TechnologyGeorgia
  2. 2.Dept. of Computer ScienceNational University of SingaporeSingapore

Personalised recommendations