Abstract
Usually, self-timed modules for asynchronous system design are realized by means of dynamic logic circuits. Moreover, in order to easily detect the end-completion, dual-rail encoding is preferred. Therefore, dynamic differential logic circuits (such as Differential Cascode Voltage Switch Logic (DCVSL)) are widely used because they intrinsically produce both true and inverted values of the output. However, the use of dynamic logic circuits presents two main difficulties: i) design and testing is more complex, ii) often it is not possible to use standard design methodology. This paper presents a new static logic VLSI implementation of a high-speed self-timed adder based on the statistical carry look-ahead addition technique. A 56-bit adder designed in this way has been realized using 0.6μm AMS Standard Cells. It requires about 0.6mm2 silicon area, has an average addition of about 4 ns, and dissipates only 20.5 mW in the worst case.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Hauck, S.: Asynchronous design methodologies: an overview. Proceedings of IEEE 83 (1995) pp. 69–93
Van Berkel, C.H., Josephs, M.B., Nowick, S.M.: Scanning the technology: Application of asynchronous system. Proceedings of IEEE 87 (1999) pp. 223–233
Ruiz, G.A.: Evaluation of three 2-bit CMOS adders in DCVS logic for self-timed circuits.IEEE J. Solid State Circuits 33 (1998) pp. 604–613
Kinniment, D.J.: An evaluation of asynchronous addition. IEEE Trans. on VLSI 4(1996) pp. 137–140
Kinniment, D.J.: A comparison of power consumption in some CMOS adder circuits. Proc. of PATMOS Conf. (1995)
De Gloria, A., Olivieri M.: Statistical carry look-ahead adders. IEEE Trans. on Comp. 45 (1996) pp.340–347
Corsonello, P., Perri, S., Cocorullo, G.: A new high performance circuit for statistical carrylook-ahead addition. Int. J. of Electronics 86, (1999) pp. 713–722
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2000 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Corsonello, P., Perri, S., Cocorullo, G. (2000). VLSI Implementation of a Low-Power High-Speed Self-Timed Adder. In: Soudris, D., Pirsch, P., Barke, E. (eds) Integrated Circuit Design. PATMOS 2000. Lecture Notes in Computer Science, vol 1918. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45373-3_20
Download citation
DOI: https://doi.org/10.1007/3-540-45373-3_20
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-41068-3
Online ISBN: 978-3-540-45373-4
eBook Packages: Springer Book Archive