Abstract
The integrated circuits design flow is rapidly moving towards higher description levels. However, test-related activities are lacking behind this trend, mainly since effective fault models and test signals generators are still missing. This paper proposes ARPIA, a new simulation-based evolutionary test generator. ARPIA adopts an innovative high-level fault model that enables efficient fault simulation and guarantees good correlation with gate-level results. The approach exploits an evolutionary algorithm to drive the search of effective patterns within the gigantic space of all possible signal sequences. ARPIA operates on register-transfer level VHDL descriptions and generates effective test patterns. Experimental results show that the achieved results are comparable or better than those obtained by high-level similar approaches or even by gate-level ones.
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© 2001 Springer-Verlag Berlin Heidelberg
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Corno, F., Cumani, G., Sonza Reorda, M., Squillero, G. (2001). ARPIA: A High-Level Evolutionary Test Signal Generator. In: Boers, E.J.W. (eds) Applications of Evolutionary Computing. EvoWorkshops 2001. Lecture Notes in Computer Science, vol 2037. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45365-2_31
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DOI: https://doi.org/10.1007/3-540-45365-2_31
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