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Using Formal Verification Techniques to Reduce Simulation and Test Effort

  • O. Laurent
  • P. Michel
  • V. Wiels
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2021)

Abstract

This paper describes an experiment in using formal methods in an industrial context. The goal is to use formal verification techniques in order to alleviate the simulation and test activities. The application is a flight control computer of the Airbus A340.

Keywords

Model Check Industrial Context Main Node Redundancy Property Transmitted Order 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • O. Laurent
    • 1
  • P. Michel
    • 2
  • V. Wiels
    • 2
  1. 1.EADS-Airbus SA, A/BTE/SY/MSToulouse cedex 03France
  2. 2.ONERA-CERT/DTIMToulouse Cedex 4France

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