Coverage Directed Generation of System-Level Test Cases for the Validation of a DSP System

  • Laurent Arditi
  • Hédi Boufaïed
  • Arnaud Cavanié
  • Vincent Stehlé
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2021)


We propose a complete methodology for the automatic generation of test cases in the context of digital circuit validation. Our approach is based on a software model of the system to verify in which some modules are written in the Esterel language. An initial test suite is simulated and the state coverage is computed. New test sequences are automatically generated to reach the missing states. We then convert those sequences into system-level test cases (i.e. instruction sequences) by a technique called “pipeline inversion”. The method has been applied for the functional validation of an industrial DSP system giving promising results.


Test Sequence Finite State Machine Missing State Linear Temporal Logic Reachable State 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Laurent Arditi
    • 1
  • Hédi Boufaïed
    • 1
  • Arnaud Cavanié
    • 2
  • Vincent Stehlé
    • 2
  1. 1.Texas Instruments FranceVilleneuve LoubetFrance
  2. 2.Esterel TechnologiesVilleneuve LoubetFrance

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