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Comprehensive Redundant Load Elimination for the IA-64 Architecture

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Languages and Compilers for Parallel Computing (LCPC 1999)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1863))

Abstract

For IA-64 architecture, a compiler can aggressively utilize control and data speculation to increase instruction-level parallelism. Aggressive speculation normally generates many speculative (control-speculative) and advanced (data-speculative) loads with the same addresses. Traditional redundant load elimination handles only regular loads. It cannot be straightforwardly applied to removing speculative and advanced loads. In this paper, we present a framework for comprehensive redundant load elimination, which correctly handles all six types of the following loads: regular loads, advanced loads, check loads, check advanced loads, speculative loads, and speculative advanced loads. Our preliminary experimental results demonstrate that it is important to perform comprehensive redundant load elimination in a compiler for architectures supporting control and data speculation.

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References

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© 2000 Springer-Verlag Berlin Heidelberg

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Wu, Y., Lee, Yf. (2000). Comprehensive Redundant Load Elimination for the IA-64 Architecture. In: Carter, L., Ferrante, J. (eds) Languages and Compilers for Parallel Computing. LCPC 1999. Lecture Notes in Computer Science, vol 1863. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44905-1_4

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  • DOI: https://doi.org/10.1007/3-540-44905-1_4

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-67858-8

  • Online ISBN: 978-3-540-44905-8

  • eBook Packages: Springer Book Archive

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