Abstract
In this paper, we propose reconfigurable, low-cost and readily available hardware architecture for an artificial neuron. This is used to build a feed-forward artificial neural network. For this purpose, we use field- programmable gate arrays i.e. FPGAs. However, as the state-of-the-art FPGAs still lack the gate density necessary to the implementation of large neural networks of thousands of neurons, we use a stochastic process to implement the computation performed by a neuron. The multiplication an addition of stochastic values is simply implemented by an ensemble of XNOR and AND gates respectively.
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© 2003 Springer-Verlag Berlin Heidelberg
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Nedjah, N., de Macedo Mourelle, L. (2003). Reconfigurable Hardware Architecture for Compact and Efficient Stochastic Neuron. In: Mira, J., Álvarez, J.R. (eds) Artificial Neural Nets Problem Solving Methods. IWANN 2003. Lecture Notes in Computer Science, vol 2687. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44869-1_3
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DOI: https://doi.org/10.1007/3-540-44869-1_3
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