Abstract
A high speed 64-bit dynamic adder, the Adelaide-Delft Threshold Logic Adder (A-DELTA), is presented. The adder is based on a hybrid carry-lookahead/carry-select scheme using threshold logic and conventional CMOS logic. A-DELTA was designed and simulated in a 0.35 μm process. The worst case critical path latency is 670 ps, which is shown to be on average 30% faster than previously proposed high speed Boolean dynamic logic adders while at the same time reducing the transistor count on average by over 30% compared to the same adders.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
Özdemir, H., Kepkep, A., Pamir, B., Leblebici, Y., Ciliniroglu, U.: A capacitive threshold-logic gate. IEEE JSSC 31 (1996) 1141–1149
Celinski, P., Löpez, J.F., Al-Sarawi, S., Abbott, D.: Low power, high speed, charge recycling CMOS threshold logic gate. IEE Electronics Letters 37 (2001) 1067–1069
Padure, M., Cotofana, S., Vassiliadis, S.: A low-power threshold logic family. In: Proc. IEEE International Conference on Electronics, Circuits and Systems. (2002) 657–660
Padure, M., Cotofana, S., Vassiliadis, S.: High-speed hybrid Threshold-Boolean logic counters and compressors. In: Proceedings of the 45th IEEE International Midwest Symposium on Circuits and Systems. (2002) 457–460
Leblebici, Y., Özdemir, H., Kepkep, A., Ciliniroglu, U.: A compact high-speed (31-5) parallel counter circuit based on capacitive threshold-logic gates. IEEE JSSC 31 (1996) 1177–1183
Celinski, P., Lopez, J.F., Al-Sarawi, S., Abbott, D.: Low depth carry lookahead addition using charge recycling threshold logic. In: Proc. IEEE International Symposium on Circuits and Systems, Phoenix (2002) 469–472
Vassiliadis, S., Cotofana, S., Bertels, K.: 2-1 addition and related arithmetic operations with threshold logic. IEEE Trans. Computers 45 (1996) 1062–1067
Rabaey, J.M.: Digital Integrated Circuits, A Design Perspective. Prentice Hall, New Jersey, USA (1996)
Ho, R., Mai, K.W., Horowitz, M.: The future of wires. Proceedings of the IEEE 89 (2001) 490–504
Naziger, S.: A sun-nanosecond 0.5_m 64b adder design. In: International Solid State Circuits Conference Digest of Technical Papers, IEEE (1996) 362–363
Woo, R., Lee, S.J., Yoo, H.J.: A 670 ps, 64bit dynamic low-power adder design. In: Proceedings of the International Symposium on Circuits and Systems, Switzerland, IEEE (2000) I28–I31
Sun, X., Mao, Z., Lai, F., Ye, Y.: A high speed 0.25_m 64-bit CMOS adder design. In: Proceedings of ASIC, IEEE (2001) 581–583
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Celinski, P., Cotofana, S.D., Abbott, D. (2003). A-DELTA: A 64-bit High Speed, Compact, Hybrid Dynamic-CMOS/Threshold-Logic Adder. In: Mira, J., Álvarez, J.R. (eds) Artificial Neural Nets Problem Solving Methods. IWANN 2003. Lecture Notes in Computer Science, vol 2687. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44869-1_10
Download citation
DOI: https://doi.org/10.1007/3-540-44869-1_10
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-40211-4
Online ISBN: 978-3-540-44869-3
eBook Packages: Springer Book Archive