Abstract
In this paper we present a functional model of spiking neuron intended for hardware implementation. The model allows the design of speed- and/or area-optimized architectures. Some features of biological spiking neurons are abstracted, while preserving the functionality of the network, in order to define an architecture easily implementable in hardware, mainly in field programmable gate arrays (FPGA). The model permits to optimize the architecture following area or speed criteria according to the application. In the same way, several parameters and features are optional, so as to allow more biologically plausible models by increasing the complexity and hardware requirements of the model. We present the results of three example applications performed to verify the computing capabilities of a simple instance of our model.
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Upegui, A., Peña-Reyes, C.A., Sanchez, E. (2003). A functional spiking neuron hardware oriented model. In: Mira, J., Álvarez, J.R. (eds) Computational Methods in Neural Modeling. IWANN 2003. Lecture Notes in Computer Science, vol 2686. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44868-3_18
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DOI: https://doi.org/10.1007/3-540-44868-3_18
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