Abstract
Energy dissipation is a critical concern for battery-powered embedded systems. Memory energy contributes significantly to overall energy in data intensive applications. Low power memory systems are being designed that support multiple power states of memory banks. In low power states, energy dissipation is reduced but time to access memory is increased. We abstract an energy model for the memory system and exploit it to develop algorithmic techniques for memory energy reduction. This is achieved by exploring the structure and data access pattern of a given algorithm to devise memory power management schedules. We illustrate our approach through two well-known embedded benchmarks — Matrix Multiplication and Fast Fourier Transform. The optimality of our schemes is discussed using information theoretic lower bounds on memory energy. Simulations demonstrate that significant energy reduction can be achieved by using our approach over state-of-the-art implementations.
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Singh, M., Prasanna, V.K. (2003). Algorithmic Techniques for Memory Energy Reduction. In: Jansen, K., Margraf, M., Mastrolilli, M., Rolim, J.D.P. (eds) Experimental and Efficient Algorithms. WEA 2003. Lecture Notes in Computer Science, vol 2647. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44867-5_20
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DOI: https://doi.org/10.1007/3-540-44867-5_20
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