Typing the ISA to Cluster the Processor

Abstract

In this paper we propose a new separation of the processor units to avoid interunits communications for instruction dispatch, memory accesses and control flow computations. The motivation comes from the increasing importance of interchip signalling delays. The technique consists in separating the instruction set into types, e.g. integer, floating point and graphic, and the die into corresponding units, each including a private pc, an instruction cache, a prediction unit, a branch unit, a load/store unit and a data cache. Every type is able to fully handle data and pointer computations as well as typed address pointers. Hence the integer machine, the floating point one and the graphical one are very independent machines requiring no inter-machine communications. We justify our proposal by showing that the main communication paths can be highly reduced in length. We show that the fetch path length can be divided by 2, the data load path length can be decreased of 1/3 and computation units interconnection paths can be highly simplified, serving only for conversion purpose.