Demonstrating Real-time JPEG Image Compression-Decompression using Standard Component IP Cores on a Programmable Logic based Platform for DSP and Image Processing

Abstract

This paper describes the successful implementation of a hardware demonstrator for real-time JPEG standard colour image compression and decompression at picture refresh rates up to 25 frames per second using an FPGA-centric processing platform and design-reusable application-specific IP cores. The FPL device programming netlists for both JPEG encode and decode are directly derived from commercially available semiconductor Intellectual Property (IP Core) designs for Motion-JPEG applications; the target FPL devices form the core processing element in a commercial off-the-shelf reconfigurable module-based hardware platform for DSP and image processing applications. Performance metrics are presented for Xilinx Virtex and Altera APEX devices, and compared with semicustom ASIC implementations.