Abstract
In this paper, we focus on system level-optimizations for automatic parallelization of nested loop on Reconfigurable Accelerators. Specifically, as off-chip bandwidth plays a major role in total performances for such implementations, we propose some partitioning techniques based on loop tiling which can take advantage of the hierarchically structured RA memory systems.
Supported in part by IFCPAR project 1802-1: CORCoP Compilation and Optimization for Reconfigurable Co-Processors
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© 2001 Springer-Verlag Berlin Heidelberg
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Derrien, S., Rajopadhye, S. (2001). Loop Tiling for Reconfigurable Accelerators. In: Brebner, G., Woods, R. (eds) Field-Programmable Logic and Applications. FPL 2001. Lecture Notes in Computer Science, vol 2147. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44687-7_41
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DOI: https://doi.org/10.1007/3-540-44687-7_41
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