Abstract
Message sequencing and channel assignment are two important aspects to consider in optimizing the performance of Wavelength Division Multiplexing (WDM) networks. A scheduling technique, Multiple-Messages-per-Node with Shortest Job First priority (MMN-SJF), has been proposed to tackle these two areas simultaneously and offers a globally optimizing approach to scheduling. In this paper, a reconfigurable testbed consisting of several interconnected FPGAs for analyzing such scheduling algorithms is introduced and in particular, a prototype scheduler is developed to investigate the implementation and hardware complexity associated with MMN-SJF. We find that the MMN-SJF scheduling technique can be implemented cost effectively and with only simple logic blocks.
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References
B. Hamidzadeh, M. Maode, and M. Hamdi, “Message Sequencing Techniques for On-Line Scheduling in WDM Networks,” Proc. IEEE Globecom’ 97, June 1997.
B. Hamidzadeh, M. Maode, and M. Hamdi, “Efficient Sequencing Techniques for Variable-Length Messages in WDM Networks” Journal of Lightwave Technology, Vol. 17, No. 8, pp. 1309–1319, August 1999.
Altera Corporation, Datasheet: FLEX 10K Embedded Programmable Logic Family version 4.01, June 1999.
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© 2000 Springer-Verlag Berlin Heidelberg
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Cheng, W.W., Wilton, S.J., Hamidzadeh, B. (2000). FPGA Implementation of a Prototype WDM On-Line Scheduler. In: Hartenstein, R.W., Grünbacher, H. (eds) Field-Programmable Logic and Applications: The Roadmap to Reconfigurable Computing. FPL 2000. Lecture Notes in Computer Science, vol 1896. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44614-1_82
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DOI: https://doi.org/10.1007/3-540-44614-1_82
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