Altera Corporation, 2610 Orchard Parkway, San Jose, CA 95134-2020. APEX Device Family
, March 1999. http://www.altera.com/html/products/apex.html
Gordon Brebner. TheSwappable Logic Unit:a Paradigm forVirtual Hardware. In Proceedings of the 5th IEEE Symposium on FPGAs for Custom Computing Machines (FCCM’97), pages 77–86, April 1997.
Joseph T. Buck. Scheduling Dynamic Dataflow Graphs with Bounded Memory using the Token Flow Model.
PhD thesis, University of California, Berkeley, 1993. ERL Technical Report 93/69.Google Scholar
David E. Culler, Seth C. Goldstein, Klaus E. Schauser, and Thorsten von Eicken. TAM — A Compiler Controlled Threaded Abstract Machine. Journal of Parallel and Distributed Computing, June 1993.
Jack B. Dennis. Data Flow Supercomputers. Computer, 13:48–56, November 1980.
Seth C. Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, and Ronald Laufer. PipeRench: a Coprocessor for Streaming Multimedia Acceleration. In Proceedings of the 26th International Symposium on Computer Architecture (ISCA’99), pages 28–39, May 1999.
Scott Hauck, Thomas Fry, Matthew Hosler, and Jeffery Kao. The Chimaera Reconfigurable Functional Unit. In Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines, pages 87–96, April 1997.
John R. Hauser and John Wawrzynek. Garp: A MIPS Processor with a Reconfigurable Coprocessor. In Proceedings of the IEEE Symposium on Field-Programmable Gate Arrays for Custom Computing Machines, pages 12–21. IEEE, April 1997.
C. A. R. Hoare. Communicating Sequential Processes. International Series in Computer Science. Prentice-Hall, 1985.
Jeffery A. Jacob and Paul Chow. Memory Interfacing and Instruction Specification for Reconfigurable Processors. In Proceedings of the 1999 International Symposium on Field Programmable Gate Arrays (FPGA’99), pages 145–154, February 1999.
Edward A. Lee. Advanced Topics in Dataflow Computing, chapter Static Scheduling of Data-Flow Programs for DSP. Prentice Hall, 1991.
X. P. Ling and H. Amano. WASMII: a Data Driven Computer on a Virtual Hardware. In Proceedings of the IEEEWorkshop on FPGAs for Custom Computing Machines (FCCM’93), pages 33–42, April 1993.
Stylianos Perissakis, Yangsung Joo, Jinhong Ahn, André DeHon, and John Wawrzynek. Embedded DRAM for a Reconfigurable Array. In Proceedings of the 1999 Symposium on VLSI Circuits, June 1999.
Rahul Razdan and Michael D. Smith. A High-Performance Microarchitecture with Hardware-Programmable Functional Units. In Proceedings of the 27th Annual International Symposium on Microarchitecture, pages 172–180. IEEE Computer Society, November 1994.
William Tsu, Kip Macy, Atul Joshi, Randy Huang, Norman Walker, Tony Tung, Omid Rowhani, Varghese George, John Wawrzynek, and André DeHon. HSRA: High-Speed, Hierarchical Synchronous Reconfigurable Array. In Proceedings of the International Symposium on Field Programmable Gate Arrays, pages 125–134, February 1999.
John Villasenor, Chris Jones, and Brian Schoner. Video Communications using Rapidly Reconfigurable Hardware. IEEE Transactions on Circuits and Systems for Video Technology
, 5:565–567, December 1995.Google Scholar
Gregory K. Wallace. The JPEG Still Picture Compression Standard. Communications of the ACM
, 34(4):30–44, April 1991.CrossRefGoogle Scholar
Xilinx, Inc., 2100 Logic Drive, San Jose, CA 95124. Virtex Series FPGAs
, 1999. http://www.xilinx.com/products/virtex.htm