StReAm: Object-Oriented Programming of Stream Architectures Using PAM-Blox

  • Oskar Mencer
  • Heiko Hübert
  • Martin Morf
  • Michael J. Flynn
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1896)


Simplifying the programming models is paramount to the success of reconfigurable computing. We apply the principles of object-oriented programming to the design of stream architectures for reconfigurable computing. The resulting tool, StReAm, is a domain specific compiler on top of the object-oriented module generation environment PAM-Blox. Combining module generation with a high-level programming tool in C++ gives the programmer the convenience to explore the flexibility of FPGAs on the arithmetic level and write the algorithms in the same language and environment.

Stream architectures consist of the pipelined dataflow graph mapped directly to hardware. Data streams through the implementation of the dataflow graph with only minimal control logic overhead. The main advantage of stream architectures is a clock-frequency equal to the data-rate leading to very low power consumption. We show a set of benchmarks from signal processing, encryption, image processing and 3D graphics in order to demonstrate the advantages of object-oriented programming of FPGAs.


Inverse Discrete Cosine Transform Class Hierarchy Communicate Sequential Process Arithmetic Unit Template Function 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. 1.
    P. Bertin, D. Roncin, J. Vuillemin, Programmable Active Memories: A Performance Assessment, ACM FPGA, February 1992.Google Scholar
  2. 2.
    C.A.R. Hoare Communicating Sequential Processes, Prentice Hall Int., 1985.Google Scholar
  3. 3.
    Embedded Solutions Handel C,
  4. 4.
    G. DeMicheli Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.Google Scholar
  5. 5.
    W. Luk, S. McKeever, Pebble: A Language for Parametrised and Recon.gurable Hardware Design, FPL, Tallinn, Aug. 1998.Google Scholar
  6. 6.
    O. Mencer, M. Morf, M. J. Flynn, PAM-Blox: High Performance FPGA Design for Adaptive Computing, IEEE FCCM, Napa Valley, CA, 1998.Google Scholar
  7. 7.
    P. Bellows, B. Hutchings, P. Bellows, J. Hawkins, S. Hemmert, B. Nelson, M. Rytting, A CAD Suite for High-Performance FPGA Design, IEEE FCCM, Napa Valley, CA, 1999.Google Scholar
  8. 8.
    S. A. Guccione,, JBits: A Java-based Interface for Reconfigurable Computing, 2nd Annual Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), Laurel, Maryland, 1999.Google Scholar
  9. 9.
    M.B. Gokhale, J.M. Stone, NAPA C: Compiling for a Hybrid RISC/FPGA Architecture, IEEE FCCM, Napa Valley, CA, 1999.Google Scholar
  10. 10.
    R. Laufer, R. Reed Taylor, H. Schmit PCI-PipeRench and SWORDAPI: A System for Stream-based Reconfigurable Computing, IEEE FCCM, Napa Valley, CA, 1999.Google Scholar
  11. 11.
    Berkeley Brass Project, SCORE: Stream Computations Organized for Reconfigurable Execution Fast Module Mapping and Placement for Datapaths in FPGAs,
  12. 12.
    T.J. Callahan, J. Wawrzynek, Instruction-Level Parallelism for Reconfigurable Computing, FPL, Tallinn, Estonia, Aug–Sep 1998.Google Scholar
  13. 13.
    X. Lai, et. al., Markov Ciphers and Diffierential Cryptanalysis, EUROCRYPT’ 91, Lecture Notes in Computer Science 547, Springer-Verlag, 1991.Google Scholar
  14. 14.
    S. Rixner, et. al., A Bandwidth-Efficient Architecture for Media Processing, MICRO, Dallas, Nov. 1998.Google Scholar
  15. 15.
    C. Ebeling, et. al., Mapping Applications to the RaPiD Configurable Architecture, IEEE FCCM, Napa Valley, CA, 1997.Google Scholar
  16. 16.
    S. Bakshi, D.D. Gajski, Partitioning and Pipelining for Performance-Constrained Hardware/Software Systems, IEEE Transaction on VLSI Systems, Dec. 1999.Google Scholar
  17. 17.
    O. Mencer, M. Morf, M. Flynn, Hardware Software Tri-Design of Encryption for Mobile Communication Units, ICASSP, Seattle, May 1998.Google Scholar
  18. 18.
    O. Mencer, L. Séméria, M. Morf, J.M. Delosme, Application of Reconfigurable CORDIC Architectures, The Journal of VLSI Signal Processing, Special Issue: VLSI on Custom Computing Technology, Kluwer, March 2000.Google Scholar
  19. 19.
    O. Mencer, M. Platzner, Dynamic Circuit Generation for Boolean Satisfiability in an Object-Oriented Design Environment, HICSS (ConfigWare), Jan. 1999.Google Scholar
  20. 20.
    O. Mencer, Rational Arithmetic Units in Computer Systems, PhD Thesis (with M.J. Flynn), E.E. Dept., Stanford, March2000.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2000

Authors and Affiliations

  • Oskar Mencer
    • 1
  • Heiko Hübert
    • 1
  • Martin Morf
    • 1
  • Michael J. Flynn
    • 1
  1. 1.Department of Electrical EngineeringComputer Systems LaboratoryStanfordUSA

Personalised recommendations