Abstract
In this paper we present a tool which operates as a pre- and postprocessor for RTL property checking and simplifies word-level specifications before verification, thus speeding up property checking runtimes and allowing larger design sizes to be verified. The basic idea is to scale down design sizes by exploiting word-level information. BooStER implements a new technique which computes a one-to-one RTL abstraction of a digital design in which the widths of word-level signals are reduced with respect to a property, i.e. the property holds for the abstract RTL if and only if it holds for the original RTL. The property checking task is completely carried out on the scaled-down version of the design. If the property fails then the tool computes counterexamples for the original RTL from counterexamples found on the reduced model.
Chapter PDF
Similar content being viewed by others
References
A. Biere, A. Cimatti, E.M. Clarke, M. Fujita, Y. Zhu. Symbolic Model Checking Using SAT Procedures instead of BDDs. DAC’99, pages 317–320. 1999.
C.W. Barrett, D.L. Dill, J.R. Levitt. A Decision Procedure for Bit-Vector Arithmetic. DAC’98, pages 522–527. 1998.
N. Bjørner, M.C. Pichora. Deciding Fixed and Non-fixed Size Bit-vectors. TACAS’98, pages 376–392. 1998.
C.Y. Huang, K.T. Cheng. Assertion checking by combined word-level ATPG and modular arithmetic constraint-solving techniques. DAC’00, pages 118–123. 2000.
D. Cyrluk, M.O. Möller, H. Ruess. An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors. CAV’97, pages 60–71. 1997.
R. Hojati, A.J. Isles, D. Kirkpatrick, R.K. Brayton. Verification Using Uninterpreted Functions and Finite Instantiations. FMCAD’96, pages 218–232. 1996.
P. Johannsen. Scaling Down Design Sizes in Hardware Verification. Ph.D. Dissertation at the Christian-Albrechts-University of Kiel, to appear in 2001.
P. Johannsen. Computing One-to-One Minimum-Width Abstractions of Digital Designs for RTL Property Checking. Intern. Report, Siemens AG, CT-SE-4, submitted to ICCAD’01.
J.P. Marques da Silva, K.A. Sakallah. Boolean satisfiability in electronic design automation. DAC’00, pages 675–680. 2000.
A. Pnueli, Y. Rodeh, O. Shtrichman, M. Siegel. Deciding Equality Formulas by Small Domains Instantiations. CAV’99, pages 455–469. 1999.
Z. Zeng, P. Kalla, M. Ciesielski. LPSAT: A Unified Approach to RTL Satisfiability. DATE’01. 2001.
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2001 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Johannsen, P. (2001). BOOSTER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstraction. In: Berry, G., Comon, H., Finkel, A. (eds) Computer Aided Verification. CAV 2001. Lecture Notes in Computer Science, vol 2102. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-44585-4_35
Download citation
DOI: https://doi.org/10.1007/3-540-44585-4_35
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-42345-4
Online ISBN: 978-3-540-44585-2
eBook Packages: Springer Book Archive