Cache-Line Decay: A Mechanism to Reduce Cache Leakage Power

  • Stefanos Kaxiras
  • Zhigang Hu
  • Girija Narlikar
  • Rae McLellan
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2008)


Reducing the supply voltage to reduce dynamic power consumption in CMOS devices, inadvertently will lead to an exponential increase in leakage power dissipation. In this work we explore an architectural idea to reduce leakage power in data caches. Previous work has shown that cache frames are “dead” for a significant fraction of time [14]. We are exploiting this observation to turn off cache lines that are not likely to be accessed any more. Our method is simple: if a cache-line is not accessed within a fixed interval (called decay interval) we turn off its supply voltage using a gated Vdd technique introduced previously [12]. We study the effect of cache-line decay on both power consumption and performance. We find that it is possible with cache-line decay to build larger caches that dissipate less leakage power than smaller caches while yielding equal or better performance (fewer misses). In addition, because our method can dynamically trade performance for leakage power it can be adjusted according to the requirements of the application and/or the environment.


Active Ratio Data Cache Cache Line Leakage Power Cache Block 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Stefanos Kaxiras
    • 1
  • Zhigang Hu
    • 2
  • Girija Narlikar
    • 1
  • Rae McLellan
    • 1
  1. 1.Bell LaboratoriesLucent TechnologiesUSA
  2. 2.Princeton UniversityUSA

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