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Compiler-Directed Dynamic Frequency and Voltage Scheduling

  • Chung-Hsing Hsu
  • Ulrich Kremer
  • Michael Hsiao
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2008)

Abstract

Dynamic voltage and frequency scaling has been identified as one of the most effective ways to reduce power dissipation. This paper discusses a compilation strategy that identifies opportunities for dynamic voltage and frequency scaling of the CPU without significant increase in overall program execution time. The paper introduces a simple, yet effective performance model to determine an effcient CPU slow-down factor for memory bound loop computations. Simulation results of a superscalar target architecture and a program kernel compiled at different optimizations levels show the potential benefit of the proposed compiler optimization. The energy savings are reported for a hypothetical target machine with power dissipation characteristics similar to Transmeta's Crusoe TM5400 processor.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Chung-Hsing Hsu
    • 1
  • Ulrich Kremer
    • 1
  • Michael Hsiao
    • 2
  1. 1.Department of Computer ScienceRutgers UniversityNew JerseyUSA
  2. 2.Department of Electrical and Computer EngineeringRutgers UniversityNew JerseyUSA

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