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An Adaptive Issue Queue for Reduced Power at High Performance

  • Alper Buyuktosunoglu
  • Stanley Schuster
  • David Brooks
  • Pradip Bose
  • Peter Cook
  • David Albonesi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2008)

Abstract

Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. A novel circuit structure dynamically gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost negligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design).

Keywords

Energy Saving Queue Size Transmission Gate Ready Instruction Superscalar Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. 1.
    R. Kessler. The Alpha 21264 microprocessor. IEEE Micro, 19(2): 24–36, March/April 1999.Google Scholar
  2. 2.
    K. Yeager. The Mips R10000 superscalar microprocessor. IEEE Micro, 16(2): 28–41, April 1996.Google Scholar
  3. 3.
    R. Canal and A. Gonzalez. A low-complexity issue logic. Proc. ACM Int’l. Conference on Supercomputing (ICS), pp. 327–335, Santa Fe, N.M., June 2000.Google Scholar
  4. 4.
    D. Folegnani and A. Gonzalez. Reducing the power consumption of the issue logic. Proc. ISCA Workshop on Complexity-Effective Design, June 2000.Google Scholar
  5. 5.
    D. H. Albonesi. Dynamic IPC/Clock Rate Optimization. Proc. ISCA-25, pp. 282–292, June/July 1998.Google Scholar
  6. 6.
    D. H. Albonesi. The Inherent Energy Efficiency of Complexity-Adaptive Processors. Proc. ISCA Workshop on Power-Driven Microarchitecture, June 1998.Google Scholar
  7. 7.
    G. Cai. Architectural level power/performance optimization and dynamic power estimation. Proc. of the Cool Chips Tutorial, in conjunction with Micro-32, 1999.Google Scholar
  8. 8.
    S. Palacharla, N. P. Jouppi and J. E. Smith. Complexity-effective superscalar processors. Proc. ISCA-97, pp. 206–218, June 1997.Google Scholar
  9. 9.
    K. Wilcox and S. Manne. Alpha Processors: A history of power issues and a look to the future. Proc. of the Cool Chips Tutorial, in conjunction with Micro-32, 1999.Google Scholar
  10. 10.
    M. Butler and Y.N Patt. An investigation of the performance of various dynamic scheduling techniques. Proc. ISCA-92, pp. 1–9.Google Scholar
  11. 11.
    R. Balasubramonian, D.H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Dynamic Memory Hierarchy Performance Optimization. Proc. ISCA Workshop on Solving the Memory Wall Problem, June 2000.Google Scholar
  12. 12.
    R. Balasubramonian, D.H. Albonesi, A. Buyuktosunoglu, and S. Dwarkadas. Memory Hierarchy Reconfiguration for Energy and Performance in General-Purpose Processor Architectures. 33rd International Symposium on Microarchitecture, December 2000.Google Scholar
  13. 13.
    M. D. Powell, S.H. Yang, B. Falsafi, K. Roy, T. N. Vijaykumar. Gated-Vdd: A Circuit Technique to Reduce Leakage in Deep-Submicron Cache Memories. ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), 2000.Google Scholar
  14. 15.
    D. Burger and T. Austin. The Simplescalar toolset, version 2.0. Technical Report TR-97–1342, University of Wisconsin-Madison, June 1997.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Alper Buyuktosunoglu
    • 3
  • Stanley Schuster
    • 1
  • David Brooks
    • 1
    • 2
  • Pradip Bose
    • 1
  • Peter Cook
    • 1
  • David Albonesi
    • 3
  1. 1.IBM T. J. Watson Research CenterYorktown HeightsNY
  2. 2.Department of Electrical EngineeringPrinceton UniversityNJ
  3. 3.Department of Electrical and Computer EngineeringUniversity of RochesterNY

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