An Adaptive Issue Queue for Reduced Power at High Performance

  • Alper Buyuktosunoglu
  • Stanley Schuster
  • David Brooks
  • Pradip Bose
  • Peter Cook
  • David Albonesi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2008)


Increasing power dissipation has become a major constraint for future performance gains in the design of microprocessors. In this paper, we present the circuit design of an issue queue for a superscalar processor that leverages transmission gate insertion to provide dynamic low-cost configurability of size and speed. A novel circuit structure dynamically gathers statistics of issue queue activity over intervals of instruction execution. These statistics are then used to change the size of an issue queue organization on-the-fly to improve issue queue energy and performance. When applied to a fixed, full-size issue queue structure, the result is up to a 70% reduction in energy dissipation. The complexity of the additional circuitry to achieve this result is almost negligible. Furthermore, self-timed techniques embedded in the adaptive scheme can provide a 56% decrease in cycle time of the CAM array read of the issue queue when we change the adaptive issue queue size from 32 entries (largest possible) to 8 entries (smallest possible in our design).


Energy Saving Queue Size Transmission Gate Ready Instruction Superscalar Processor 
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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • Alper Buyuktosunoglu
    • 3
  • Stanley Schuster
    • 1
  • David Brooks
    • 1
    • 2
  • Pradip Bose
    • 1
  • Peter Cook
    • 1
  • David Albonesi
    • 3
  1. 1.IBM T. J. Watson Research CenterYorktown HeightsNY
  2. 2.Department of Electrical EngineeringPrinceton UniversityNJ
  3. 3.Department of Electrical and Computer EngineeringUniversity of RochesterNY

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