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Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor

  • David Brooks
  • Margaret Martonosi
  • John-David Wellman
  • Pradip Bose
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2008)

Abstract

We describe a new power-performance modeling toolkit, developed to aid in the evaluation and definition of future power-efficient, PowerPCTM processors. The base performance models in use in this project are: (a) a fast but cycle-accurate, parameterized research simulator and (b) a slower, pre-RTL reference model that models a specific high-end machine in full, latch-accurate detail. Energy characterizations are derived from real, circuit-level power simulation data. These are then combined to form higher-level energy models that are driven by microarchitecture-level parameters of interest. The overall methodology allows us to conduct power-performance tradeoff studies in defining the follow-on design points within a given product family. We present a few experimental results to illustrate the kinds of tradeoffs one can study using this tool.

Keywords

Energy Model Power Dissipation Product Family Cache Size Processor Model 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 2001

Authors and Affiliations

  • David Brooks
    • 1
  • Margaret Martonosi
    • 1
  • John-David Wellman
    • 2
  • Pradip Bose
    • 2
  1. 1.Princeton UniversityPrincetonNJ
  2. 2.IBM T.J. Watson Research CenterYorktown HeightsNY

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