Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor
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We describe a new power-performance modeling toolkit, developed to aid in the evaluation and definition of future power-efficient, PowerPCTM processors. The base performance models in use in this project are: (a) a fast but cycle-accurate, parameterized research simulator and (b) a slower, pre-RTL reference model that models a specific high-end machine in full, latch-accurate detail. Energy characterizations are derived from real, circuit-level power simulation data. These are then combined to form higher-level energy models that are driven by microarchitecture-level parameters of interest. The overall methodology allows us to conduct power-performance tradeoff studies in defining the follow-on design points within a given product family. We present a few experimental results to illustrate the kinds of tradeoffs one can study using this tool.
KeywordsEnergy Model Power Dissipation Product Family Cache Size Processor Model
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