Abstract
In this paper we present a process algebra approach for the integrated verification of correctness and performance in concurrent systems. The verification procedure is entirely performed within the Circal process algebra, without any recourse to other formalisms. Performance is characterised in terms of logical properties, which do not incorporate explicit time. Such properties are then interpreted in terms of degree of parallelism and allow the quantitative evaluation of the throughput of the system. The approach has been applied to two four-phase handshaking protocols, which are motivated by the implementation of the AMULET2 asynchronous RISC processor. Both correctness and performance properties are captured in the same verification framework and automatically proved using the Circal System.
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References
F. Bacelli et al. Synchronisation and Linearity-Algebra for Discrete Event Systems, Wiley, 1992.
A. Bailey, G. A. McCaskill and G. J. Milne. An Exercise in the Automatic Verification of Asynchronous Designs. Formal Methods in System Design, Vol. 4, No. 3, pp. 213–242, 1994.
T. Bolognesi, and E. Brinksma. Introduction to the ISO specification language LOTOS. Computer Networks and ISDN Systems, Vol. 14, No. 1, pp. 25–59, 1987.
A. Cerone, D. A. Kearney and G. J. Milne. Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems. In Proc. of the Int. Conference on Application of Concurrency to System Design,Aizu-Wakamatsu City, Japan, pp. 109–119, IEEE Comp. Soc. Press, 1998.
A. Cerone and G. J. Milne. Modelling a Subclass of CMOS Circuits using a Process Algebra. In Proc. 6th Annual Australasian Conference on Parallel and Real-Time Systems (PART’99), Melbourne, Australia, pp. 386–397, Springer-Verlag, Berlin, 1999.
T. A. Chu, C. K. C. Leung and T. S. Wanuga. A Design Methodology for Concurrent VLSI Systems. In Proc. of ICDD, pp. 407–410, 1985.
R. de Nicola and M. C. B. Hennessy. Testing Equivalence for Processes. Theoretical Computer Science, Vol. 34, No. 1/2, pp. 83–134, 1984.
S. Donatelli, J. Hillston and M. Ribaudo. Comparison of Performance Evaluation Process Algebra and Generalized Stochastic Petri Nets. In Proc. of the 6th Int. Work. on Petri Nets and Performance Models, IEEE Comp. Soc. Press, 1995.
S. B.. Furber and P. Day. Four-Phase Micropipeline Latch Control Circuit. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, Vol. 4, No. 2, pp. 247–253, 1996.
S. B. Furber and J. Lin. Dynamic Logic in Four-Phase Micropipelines. In Proc. of the 2nd Int. Symp. on Adv. Research in Asynchronous Circuits and Systems, IEEE Comp. Soc. Press, 1996.
M. J. C. Gordon and T. F. Melham. Introduction to HOL, Cambridge University Press, 1993.
C. A. R. Hoare. Communication Sequential Processes, International Series in Computer Science, Prentice Hall, 1985.
G. J. Milne. Formal Specification and Verification of Digital Systems,McGraw-Hill, 1994.
R. Milner. Communication and Concurrency, International Series in Computer Science, Prentice Hall, 1989.
F. Moller. The Semantics of Circal, Technical Report HDV-3-89, University of Strathclyde, Department of Computer Science, Glasgow, UK, 1989.
A. W. Roscoe. The Theory and Practice of Concurrency, International Series in Computer Science, Prentice Hall, 1998.
I. E. Sutherland. Micropipelines. Com. of ACM, Vol. 32, No. 6, pp. 720–738, 1989.
T. Williams. Analyzing and Improving the latency and throughput performance on self-timed pipelines and rings. In Proc. of the IEEE Int. Symp. on Circuit and Systems, New York, IEEE Comp. Soc. Press, 1992.
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Cerone, A., Milne, G.J. (2000). A Methodology for the Formal Analysis of Asynchronous Micropipelines. In: Hunt, W.A., Johnson, S.D. (eds) Formal Methods in Computer-Aided Design. FMCAD 2000. Lecture Notes in Computer Science, vol 1954. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-40922-X_16
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DOI: https://doi.org/10.1007/3-540-40922-X_16
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