Abstract
In this paper we investigate timing diagrams as a means to specify causal dependencies. We introduce a stylized graphical represen- tation of timing diagrams for which we define a formal basis. Further- more, we compare our approach with well-known approaches from the area of program verification and show the semantic relationships. The major aim we follow by this work is a seamless integration of hardware design and software development providing a common semantic basis e.g. for verification. Therefore, the semantic relationships to frameworks for program verification show that the combination of these approaches is a good starting point for further development.
Supported by the DFG under project no. NE 592/4-2.
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Fischer, J., Conrad, S. (2000). Formalizing Timing Diagrams as Causal Dependencies for Verification Purposes. In: Grieskamp, W., Santen, T., Stoddart, B. (eds) Integrated Formal Methods. IFM 2000. Lecture Notes in Computer Science, vol 1945. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-40911-4_4
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