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International Symposium on High Performance Computing

ISHPC 2000: High Performance Computing pp 120–133Cite as

Processor Mechanisms for Software Shard Memory

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Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1940))

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The M-Machine’s combined hardware-software shared-memory system provides significantly lower remote memory latencies than software DSM systems while retaining the flexibility of software DSM. This system is based around four hardware mechanisms for shared memory: status bits on individual memory blocks, hardware translation of memory addresses to home processors, fast detection of remote accesses, and dedicated thread slots for shared-memory handlers. These mechanisms have been implemented on the MAP processor, and allow remote memory references to be completed in as little as 336 cycles at low hardware cost.

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Author information

Authors and Affiliations

  1. Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, USA

    Nicholas P.

  2. Computer Systems Laboratory, Stanford University, USA

    William J. & Andrew Chang

  3. Sun Microsystems, USA

    Whay S.

  4. Department of Computer Sciences, The University of Texas at Austin, USA

    Stephen W. Keckler

Authors
  1. Nicholas P.
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  2. William J.
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  3. Whay S.
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  4. Stephen W. Keckler
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  5. Andrew Chang
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Editor information

Editors and Affiliations

  1. Departamento de Arquitectura de Computadores, Universidad Politecnica de Catalunya, Spain

    Mateo Valero

  2. Department of Information and Computer Sciences, Nara Women’s University, Japan

    Kazuki Joe

  3. Institute of Industrial Science Center for Conceptual Information Processing Research, University of Tokyo, Japan

    Masaru Kitsuregawa

  4. Graduate School of Engineering Electrical Engineering Department, University of Tokyo, Japan

    Hidehiko Tanaka

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© 2000 Springer-Verlag Berlin Heidelberg

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P., N., J., W., S., W., Keckler, S.W., Chang, A. (2000). Processor Mechanisms for Software Shard Memory. In: Valero, M., Joe, K., Kitsuregawa, M., Tanaka, H. (eds) High Performance Computing. ISHPC 2000. Lecture Notes in Computer Science, vol 1940. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-39999-2_11

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  • DOI: https://doi.org/10.1007/3-540-39999-2_11

  • Published:

  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-41128-4

  • Online ISBN: 978-3-540-39999-5

  • eBook Packages: Springer Book Archive

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