Abstract p ]For the past two decades, the emphasis in processor microarchitecture has been on instruction level parallelism (ILP) — or in increasing performance by increasing the number of “instructions per cycle”. In striving for higher ILP, there has been an ongoing evolution from pipelining to superscalar, with researchers pushing toward increasingly wide superscalar. Emphasis has been placed on wider instruction fetch, higher instruction issue rates, larger instruction windows, and increasing use of prediction and speculation. This trend has led led to very complex, hardware-intensive processors.
For the past two decades, the emphasis in processor microarchitecture has been on instruction level parallelism (ILP) — or in increasing performance by increasing the number of “instructions per cycle”. In striving for higher ILP, there has been an ongoing evolution from pipelining to superscalar, with researchers pushing toward increasingly wide superscalar. Emphasis has been placed on wider instruction fetch, higher instruction issue rates, larger instruction windows, and increasing use of prediction and speculation. This trend has led led to very complex, hardware-intensive processors.
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Smith, J.E. (2000). Instruction Level Distributed Processing: Adapting to Future Technology. In: Valero, M., Joe, K., Kitsuregawa, M., Tanaka, H. (eds) High Performance Computing. ISHPC 2000. Lecture Notes in Computer Science, vol 1940. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-39999-2_1
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