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International Workshop on Power-Aware Computer Systems

PACS 2002: Power-Aware Computer Systems pp 33–52Cite as

A Hardware Architecture for Dynamic Performance and Energy Adaptation

Part of the Lecture Notes in Computer Science book series (LNCS,volume 2325)

Abstract

Energy consumption of any component in a system may sometimes constitute just a small percentage of that of the overall system, making it necessary to address the issue of energy efficiency across the entire range of system components, from memory, to the CPU, to peripherals. Presented is a hardware architecture for detecting regions of application execution at runtime, for which there is opportunity to run a device at a slightly lower performance level, by reducing the operating frequency and voltage, to save energy. The proposed architecture, the Power Adaptation Unit (PAU) may be used to control the operating voltage of various system components, ranging from the CPU core, to memory and peripherals.

An evaluation of the tradeoffs in performance versus energy savings and hardware cost of the PAU is conducted, along with results on its efficacy for a set of benchmarks. It is shown that on the average, a single entry PAU provides energy savings of 27%, with a corresponding performance degradation of 0.75% for the SPEC CPU 2000 integer and floating point benchmarks investigated.

Keywords

  • Energy Saving
  • Memory Access
  • Clock Cycle
  • Performance Degradation
  • Hardware Architecture

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Author information

Authors and Affiliations

  1. Dept. of ECE, Carnegie Mellon University, Pittsburgh, PA, 15213

    Phillip Stanley-Marbell

  2. Dept. of ECE, Virginia Tech, Blacksburg, VA, 24061

    Michael S. Hsiao

  3. Dept. of Computer Science, Rutgers University, Piscataway, NJ, 08854

    Ulrich Kremer

Authors
  1. Phillip Stanley-Marbell
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  2. Michael S. Hsiao
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  3. Ulrich Kremer
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Editor information

Editors and Affiliations

  1. Electrical and Computer Engineering, Computer Science, Carnegie Mellon University, Hamershlag Hall A305, 5000 Frobes Ave., Pittsburgh, PA, 15213, USA

    Babak Falsafi

  2. School of Electrical and Computer Engineering, Purdue University, 1285 Electrical Engineering Building, West Lafayette, Indiana, 47907-1285, USA

    T. N. Vijaykumar

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© 2003 Springer-Verlag Berlin Heidelberg

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Stanley-Marbell, P., Hsiao, M.S., Kremer, U. (2003). A Hardware Architecture for Dynamic Performance and Energy Adaptation. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2002. Lecture Notes in Computer Science, vol 2325. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36612-1_3

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  • DOI: https://doi.org/10.1007/3-540-36612-1_3

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-01028-9

  • Online ISBN: 978-3-540-36612-6

  • eBook Packages: Springer Book Archive

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