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Early-Stage Definition of LPX: A Low Power Issue-Execute Processor

Part of the Lecture Notes in Computer Science book series (LNCS,volume 2325)

Abstract

We present the high-level microarchitecture of LPX: a low-power issue-execute processor prototype that is being designed by a joint industry-academia research team. LPX implements a very small subset of a RISC architecture, with a primary focus on a vector (SIMD) multimedia extension. The objective of this project is to validate some key new ideas in power-aware microarchitecture techniques, supported by recent advances in circuit design and clocking.

Keywords

  • Data Cache
  • Test Chip
  • Loop Trace
  • Loop Buffer
  • Cache Mode

These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Bose, P. et al. (2003). Early-Stage Definition of LPX: A Low Power Issue-Execute Processor. In: Falsafi, B., Vijaykumar, T.N. (eds) Power-Aware Computer Systems. PACS 2002. Lecture Notes in Computer Science, vol 2325. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36612-1_1

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  • DOI: https://doi.org/10.1007/3-540-36612-1_1

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  • Print ISBN: 978-3-540-01028-9

  • Online ISBN: 978-3-540-36612-6

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