Abstract
Most evolutionary approaches to fault recovery in FPGAs focus on evolving alternative logic configurations as opposed to evolving the intra-cell routing. Since the majority of transistors in a typical FPGA are dedicated to interconnect, nearly 80% according to one estimate, evolutionary fault-recovery systems should benefit by accommodating routing. In this paper, we propose an evolutionary fault-recovery system employing a genetic representation that takes into account both logic and routing configurations. Experiments were run using a software model of the Xilinx Virtex FPGA. We report that using four Virtex combinational logic blocks, we were able to evolve a 100% accurate quadrature decoder finite state machine in the presence of a stuck-at-zero fault.
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Lohn, J., Larchev, G., DeMara, R. (2003). A Genetic Representation for Evolutionary Fault Recovery in Virtex FPGAs. In: Tyrrell, A.M., Haddow, P.C., Torresen, J. (eds) Evolvable Systems: From Biology to Hardware. ICES 2003. Lecture Notes in Computer Science, vol 2606. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36553-2_5
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DOI: https://doi.org/10.1007/3-540-36553-2_5
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