A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs

  • Prithviraj Banerjee
  • Malay Haldar
  • Anshuman Nayak
  • Victor Kim
  • Debabrata Bagchi
  • Satrajit Pal
  • Nikhil Tripathi
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 2571)


This paper describes how fine grain parallelism can be exploited using a behavioral synthesis tool called AccelFPGA which reads in high-level descriptions of DSP applications written in MATLAB, and automatically generates synthesizable RTL models in VHDL or Verilog. The RTL models can be synthesized using commercial logic synthesis tools and place and route tools onto FPGAs. The paper describes how powerful directives are used to provide high-level architectural tradeoffs by exploiting fine grain parallelism, pipelining, memory mapping and tiling for the DSP designer. Experimental results are reported with the AccelFPGA version 1.4 compiler on a set of 8 MATLAB benchmarks that are mapped onto the Xilinx Virtex II FPGAs.


Digital Signal Processing Finite Impulse Response Finite Impulse Response Filter Register Transfer Level Hardware Description Language 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.


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Copyright information

© Springer-Verlag Berlin Heidelberg 2002

Authors and Affiliations

  • Prithviraj Banerjee
    • 1
  • Malay Haldar
    • 1
  • Anshuman Nayak
    • 1
  • Victor Kim
    • 1
  • Debabrata Bagchi
    • 1
  • Satrajit Pal
    • 1
  • Nikhil Tripathi
    • 1
  1. 1.AccelChip, Inc.Schaumburg

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