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A Programming Approach to the Design of Asynchronous Logic Blocks

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Concurrency and Hardware Design

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 2549))

Abstract

Delay-Insensitive Sequential Processes is a structured, parallel programming language. It facilitates the clear, succinct and precise specification of the way an asynchronous logic block is to interact with its environment. Using the tool di2pn, such a specification can be automatically translated into a Petri net. Using the tool petrify, the net can be automatically validated (for freedom from deadlock and interference, and for implementability as a speed-independent circuit) and asynchronous logic can be automatically synthesised.

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Authors and Affiliations

  1. Centre for Concurrent Systems and Very Large Scale Integration School of Computing, Information Systems and Mathematics, South Bank University, 103 Borough Road, SE1 0AA, London, UK

    Mark B. Josephs & Dennis P. Furey

Authors
  1. Mark B. Josephs
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  2. Dennis P. Furey
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Editor information

Editors and Affiliations

  1. Department of Software, Technical University of Catalonia, Campus Nord, Mòdul C5, Jordi Girona Salgado 1-3, 08034, Barcelona, Spain

    Jordi Cortadella

  2. School of Electrical, Electronic and Computer Engineering, University of Newcastle, Newcastle upon Tyne, NE1 7RU, UK

    Alex Yakovlev

  3. Center for Natural Computing, Leiden University, Niels Bohrweg 1, 2333, Leiden, CA, The Netherlands

    Grzegorz Rozenberg

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© 2002 Springer-Verlag Berlin Heidelberg

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Josephs, M.B., Furey, D.P. (2002). A Programming Approach to the Design of Asynchronous Logic Blocks. In: Cortadella, J., Yakovlev, A., Rozenberg, G. (eds) Concurrency and Hardware Design. Lecture Notes in Computer Science, vol 2549. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-36190-1_2

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  • DOI: https://doi.org/10.1007/3-540-36190-1_2

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-00199-7

  • Online ISBN: 978-3-540-36190-9

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